View TDA9875AV2_5650678.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

d a t a sh eet product speci?cation supersedes data of 1998 aug 13 file under integrated circuits, ic02 1999 dec 20 integrated circuits tda9875a digital tv sound processor (dtvsp)
1999 dec 20 2 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a contents 1 features 1.1 demodulator and decoder section 1.2 dsp section 1.3 analog audio section 2 general description 2.1 supported standards 3 ordering information 4 block diagram 5 pinning 6 functional description 6.1 demodulator and decoder section 6.2 digital signal processing 6.3 analog audio section 7 limiting values 8 thermal characteristics 9 characteristics 10 i 2 c-bus control 10.1 introduction 10.2 power-up state 10.3 slave receiver mode 10.4 slave transmitter mode 10.5 expert mode 11 i 2 s-bus description 12 application information 13 package outlines 14 soldering 14.1 introduction 14.2 through-hole mount packages 14.3 surface mount packages 14.4 suitability of ic packages for wave, reflow and dipping soldering methods 15 definitions 16 life support applications 17 purchase of philips i 2 c components
1999 dec 20 3 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 1 features 1.1 demodulator and decoder section sound if (sif) input switch e.g. to select between terrestrial tv sif and sat sif sources sif agc with 24 db control range sif 8-bit analog-to-digital converter (adc) differential quadrature phase shift keying (dqpsk) demodulation for different standards, simultaneously with 1-channel fm demodulation near instantaneous companded audio multiplex (nicam) decoding (b/g, i and l standard) two-carrier multistandard fm demodulation (b/g, d/k and m standard) decoding for three analog multi-channel systems (a2, a2+ and a2*) and satellite sound optional am demodulation for system l, simultaneously with nicam programmable identification (b/g, d/k and m standard) and different identification times. 1.2 dsp section digital crossbar switch for all digital signal sources and destinations control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft mute plop-free volume control automatic volume level (avl) control adaptive de-emphasis for satellite programmable beeper monitor selection for fm/am dc values and signals, with peak detection option i 2 s-bus interface for a feature extension (e.g. dolby pro logic) with matrix, level adjust and mute. 1.3 analog audio section analog crossbar switch with inputs for mono and stereo (also applicable as scart 3 input), scart 1 input/output, scart 2 input/output and line output user defined full-level/ - 3 db scaling for scart outputs output selection of mono, stereo, dual a/b, dual a or dual b 20 khz bandwidth for scart-to-scart copies standby mode with function for scart copies dual audio digital-to-analog converter (dac) from dsp to analog crossbar switch, bandwidth 15 khz dual audio adc from analog inputs to dsp two dual audio dacs for loudspeaker (main) and headphone (auxiliary) outputs; also applicable for l, r, c and s in the dolby pro logic mode with feature extension. 2 general description the tda9875a is a single-chip digital tv sound processor (dtvsp) for analog and digital multi-channel sound systems in tv sets and satellite receivers. 2.1 supported standards the multistandard/multi-stereo capability of the tda9875a is mainly of interest in europe, but also in hong kong/peoples republic of china and south east asia. this includes b/g, d/k, i, m and l standards. in other application areas there exists only subsets of these standard combinations otherwise only single standards are transmitted. m standard is transmitted in europe by the american forces network (afn) with european channel spacing (7 mhz vhf and 8 mhz uhf) and monaural sound. the am sound of l/l accent standard is normally demodulated in the first sound if. the resulting af signal has to be entered into the mono audio input of the tda9875a. a second possibility is to use the internal am demodulator stage, however this gives limited performance. korea has a stereo sound system similar to europe and is supported by the tda9875a. the differences include deviation, modulation contents and identification. it is based on m standard. an overview of the supported standards and sound systems and their key parameters is given in table 1. the analog multi-channel sound systems (a2, a2+ and a2*) are 2-carrier systems (2cs).
1999 dec 20 4 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 2.1.1 a nalog 2- carrier systems table 1 frequency modulation table 2 identi?cation for a2 systems 2.1.2 2- carrier systems with nicam table 3 nicam notes 1. see ebu specification or equivalent specification. 2. not yet defined. standard sound system carrier frequency (mhz) fm deviation (khz) modulation bandwidth/ de-emphasis (khz/ m s) nom. max. over sc1 sc2 m mono 4.5 15 25 50 mono - 15/75 m a2+ 4.5/4.724 15 25 50 1 2 (l+r) 1 2 (l - r) 15/75 (korea) b/g a2 5.5/5.742 27 50 80 1 2 (l + r) r 15/50 i mono 6.0 27 50 80 mono - 15/50 d/k a2 6.5/6.742 27 50 80 1 2 (l + r) r 15/50 d/k a2* 6.5/6.258 27 50 80 1 2 (l + r) r 15/50 parameter a2/a2* a2+ (korea) pilot frequency 54.6875 khz = 3.5 line frequency 55.0699 khz = 3.5 line frequency stereo identi?cation frequency dual identi?cation frequency am modulation depth 50% 50% standard sc1 sc2 nicam (mhz) de- emphasis roll- off (%) nicam coding frequency (mhz) type modulation index (%) deviation (khz) nom. max. nom. max. b/g 5.5 fm -- 27 50 5.85 j17 40 note 1 i 6.0 fm -- 27 50 6.552 j17 100 note 1 d/k 6.5 fm -- 27 50 5.85 j17 40 note 2 l 6.5 am 54 100 -- 5.85 j17 40 note 1 117.5 hz line frequency 133 ------------------------------------ - = 149.9 hz line frequency 105 ------------------------------------ - = 274.1 hz line frequency 57 ------------------------------------ - = 276.0 hz line frequency 57 ------------------------------------ - =
1999 dec 20 5 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 2.1.3 s atellite systems an important specification for satellite tv reception is the astra specification . the tda9875a is suited for the reception of astra and other satellite signals. table 4 fm satellite sound notes 1. for other satellite systems, frequencies of e.g. 5.80, 6.60 or 6.65 mhz can also be received. 2. a de-emphasis of 60 m s, or in accordance with j17, is available. 3. m/st/d = mono, stereo or dual language sound. 4. adaptive de-emphasis is compatible to transmitter specification. 3 ordering information carrier type carrier frequency (mhz) modulation index maximum fm deviation (khz) modulation bandwidth/ de-emphasis (khz/ m s) main 6.50 (1) 0.26 85 mono 15/50 (2) sub 7.02/7.20 0.15 50 m/st/d (3) 15/adaptive (4) sub 7.38/7.56 sub 7.74/7.92 sub 8.10/8.28 type number package name description version tda9875a sdip64 plastic shrink dual in-line package; 64 leads (750 mil) sot274-1 tda9875ah qfp64 plastic quad ?at package; 64 leads (lead length 1.6 mm); body 14 14 2.7 mm sot393-1
1999 dec 20 6 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 4 block diagram handbook, full pagewidth mhb598 i 2 c-bus interface input switch agc, adc fm (am) demodulation supply sound if (sif) identification a2/satellite decoder audio processing supply scart, dac, adc level adjust nicam demodulation nicam decoder level adjust peak detection adc (2) dac (2) dac (2) test mol dac (2) analog crossbar switch clock sif2 sif1 9 (1) 20 (12) 10 (2) 12 (4) 3 (59) 13 (5) 4 (60) 5 (61) p1 p2 addr1 addr2 18 (10) xtali 19 (11) xtalo 21 (13) sysclk scl sda i 2 s-bus interface 27 (19) 26 (18) 25 (17) 24 (16) 22 (14) 23 (15) sdi1 sdi2 sdo1 sdo2 sck ws digital supply digital select 15 (7) 64 (56) 35 (27) 17 (9) 16 (8) v ddd1 v ddd2 v ssd3 v ssd4 creset 14 (6) 49 (41) v ssd1 v ssd2 28 (20) v ref3 v ref(n) v ref(p) v dec2 v dda pcapl pcapr 30 (22) (51) 59 (30) 38 (46) 54 pclk nicam (57) 1 (58) 2 lol lor scol2 scor2 scol1 scor1 (44) 52 (43) 51 (54) 62 (55) 63 (40) 48 (39) 47 i ref (64) 8 v ref1 (3) 11 v ssa1 (62) 6 v dec1 (63) 7 monoin extil extir scil2 scir2 scil1 (23) 31 (29) 37 (21) 29 (24) 32 (28) 36 (26) 34 scir1 (25) 33 (47) 55 (31) 39 (32) 40 (53) 61 mor (52) 60 auxol (50) 58 auxor (49) 57 test2 test1 i.c. (34) 42 i.c. (33) 41 i.c. (36) 44 i.c. (37) 45 v ssa3 v ssa2 v ref2 (38) 46 (45) 53 (35) 43 (48) 56 v ssa4 (42) 50 tda9875a ( tda9875ah ) fig.1 block diagram. the pin numbers given in parenthesis refer to the tda9875ah version.
1999 dec 20 7 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 5 pinning symbol pin pin type (1) description tda9875a tda9875ah pclk 1 57 o nicam clock output at 728 khz nicam 2 58 o serial nicam data output at 728 khz addr1 3 59 i i 2 c-bus slave address input 1 scl 4 60 i i 2 c-bus clock input sda 5 61 i/o i 2 c-bus data input/output v ssa1 6 62 s supply ground 1; analog front-end circuitry v dec1 763 - supply voltage decoupling 1; analog front-end circuitry i ref 864 - resistor for reference current generator; analog front-end circuitry p1 9 1 i/o general purpose input/output pin 1 sif2 10 2 i sound if input 2 v ref1 11 3 - reference voltage 1; analog front-end circuitry sif1 12 4 i sound if input 1 addr2 13 5 i i 2 c-bus slave address input 2 v ssd1 14 6 s supply ground 1; digital circuitry v ddd1 15 7 s digital supply voltage 1; digital circuitry creset 16 8 - capacitor for power-on reset v ssd4 17 9 s supply ground 4; digital circuitry xtali 18 10 i crystal oscillator input xtalo 19 11 o crystal oscillator output p2 20 12 i/o general purpose input/output pin 2 sysclk 21 13 o system clock output sck 22 14 i/o i 2 s-bus clock input/output ws 23 15 i/o i 2 s-bus word select input/output sdo2 24 16 o i 2 s-bus data output 2 (i 2 s2 output) sdo1 25 17 o i 2 s-bus data output 1 (i 2 s1 output) sdi2 26 18 i i 2 s-bus data input 2 (i 2 s2 input) sdi1 27 19 i i 2 s-bus data input 1 (i 2 s1 input) test1 28 20 i test pin 1; connected to v ssd1 for normal operating mode monoin 29 21 i audio mono input test2 30 22 i test pin 2; connected to v ssd1 for normal operating mode extir 31 23 i external audio input right channel extil 32 24 i external audio input left channel scir1 33 25 i scart 1 input right channel scil1 34 26 i scart 1 input left channel v ssd3 35 27 s supply ground 3; digital circuitry scir2 36 28 i scart 2 input right channel scil2 37 29 i scart 2 input left channel v dec2 38 30 - supply voltage decoupling 2; audio analog-to-digital converter circuitry
1999 dec 20 8 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a notes 1. pin type: i = input, o = output, s = supply. 2. test pin: cmos level input; pull-up resistor; can be connected to v ss . 3. test pin: cmos 3-state stage; can be connected to v ss . v ref(p) 39 31 - positive reference voltage; audio analog-to-digital converter circuitry v ref(n) 40 32 - reference voltage ground; audio analog-to-digital converter circuitry i.c. 41 33 - internally connected; note 2 i.c. 42 34 - internally connected; note 3 v ssa2 43 35 s supply ground 2; audio analog-to-digital converter circuitry i.c. 44 36 - internally connected; note 3 i.c. 45 37 - internally connected; note 2 v ref2 46 38 - reference voltage 2; audio analog-to-digital converter circuitry scor1 47 39 o scart 1 output right channel scol1 48 40 o scart 1 output left channel v ssd2 49 41 s supply ground 2; digital circuitry v ssa4 50 42 s supply ground 4; audio operational ampli?er circuitry scor2 51 43 o scart 2 output right channel scol2 52 44 o scart 2 output left channel v ref3 53 45 - reference voltage 3; audio digital-to-analog converter and operational ampli?er circuitry pcapr 54 46 - post-?lter capacitor pin right channel; audio digital-to-analog converter pcapl 55 47 - post-?lter capacitor pin left channel; audio digital-to-analog converter v ssa3 56 48 s supply ground 3; audio digital-to-analog converter circuitry auxor 57 49 o headphone (auxiliary) output right channel auxol 58 50 o headphone (auxiliary) output left channel v dda 59 51 s analog supply voltage; analog circuitry mor 60 52 o loudspeaker (main) output right channel mol 61 53 o loudspeaker (main) output left channel lol 62 54 o line output left channel lor 63 55 o line output right channel v ddd2 64 56 s digital supply voltage 2; digital circuitry symbol pin pin type (1) description tda9875a tda9875ah
1999 dec 20 9 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a handbook, halfpage tda9875a mhb071 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ddd2 lor lol mol mor v dda auxol auxor v ssa3 pcapl pcapr v ref3 scol2 scor2 v ssa4 v ssd2 scol1 scor1 v ref2 i.c. i.c. v ssa2 i.c. i.c. v ref(n) v ref(p) v dec2 scil2 scir2 v ssd3 scil1 scir1 pclk nicam addr1 scl sda v ssa1 v dec1 i ref p1 sif2 v ref1 sif1 addr2 v ssd1 v ddd1 creset v ssd4 xtali xtalo p2 sysclk sck ws sdo2 sdo1 sdi2 sdi1 test1 monoin test2 extir extil fig.2 pin configuration (tda9875a).
1999 dec 20 10 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a handbook, full pagewidth tda9875ah mhb599 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ssa3 pcapl pcapr v ref3 scol2 scor2 v ssa4 v ssd2 scol1 scor1 v ref2 i.c. i.c. v ssa2 i.c. i.c. p1 sif2 v ref1 sif1 addr2 v ssd1 v ddd1 creset v ssd4 xtali xtalo p2 sysclk sck ws sdo2 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 i ref v dec1 v ssa1 sda scl addr1 nicam pclk v ddd2 lor lol mol mor v dda auxol auxor sdo1 sdi2 sdi1 test1 monoin test2 extir extil scir1 scil1 v ssd3 scir2 scil2 v dec2 v ref(p) v ref(n) 49 fig.3 pin configuration (tda9875ah).
1999 dec 20 11 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 6 functional description 6.1 demodulator and decoder section 6.1.1 sif input two input pins are provided: sif1 e.g. for terrestrial tv and sif2 e.g. for a satellite tuner. for higher sif signal levels the sif input can be attenuated with an internal switchable - 10 db resistor divider. as no specific filters are integrated, both inputs have the same specification giving flexibility in application. the selected signal is passed through an agc circuit and then digitized by an 8-bit adc operating at 24.576 mhz. 6.1.2 agc the gain of the agc amplifier is controlled from the adc output by means of a digital control loop employing hysteresis. the agc has a fast attack behaviour to prevent adc overloads and a slow decay behaviour to prevent agc oscillations. for am demodulation the agc must be switched off. when switched off, the control loop is reset and fixed gain settings can be chosen (see table 15). the agc can be controlled via the i 2 c-bus. details can be found in the i 2 c-bus register definitions (see chapter 10). 6.1.3 m ixer the digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero if. a 24-bit control word for each carrier sets the required frequency. access to the mixer control word registers is via the i 2 c-bus. when receiving nicam programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency loop. 6.1.4 fm and am demodulation an fm or am input signal is fed via a band-limiting filter to a demodulator that can be used for either fm or am demodulation. apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. a stereo decoder recovers the left and right signal channels from the demodulated sound carriers. both the european and korean stereo systems are supported. 6.1.5 fm identification the identification of the fm sound mode is performed by am synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. the result is available via the i 2 c-bus interface. a selection can be made via the i 2 c-bus for b/g, d/k and m standard and for three different modes that represent different trade-offs between speed and reliability of identification. 6.1.6 nicam demodulation the nicam signal is transmitted in a dqpsk code at a bit rate of 728 kbit/s. the nicam demodulator performs dqpsk demodulation and feeds the resulting bitstream and clock signal onto the nicam decoder and, for evaluation purposes, to pins pclk and nicam. a timing loop controls the frequency of the crystal oscillator to lock the sampling rate to the symbol timing of the nicam data. 6.1.7 nicam decoder the device performs all decoding functions in accordance with the ebu nicam 728 specification . after locking to the frame alignment word, the data is descrambled by applying the defined pseudo-random binary sequence and the device will then synchronize to the periodic frame flag bit c0. bit vdsp (see section 10.4.1) indicates that the decoder has locked to the nicam data and that the data is valid sound data. the status of the nicam decoder can be read out from the nicam status register by the user (see section 10.4.2). bit osb indicates that the decoder has locked to the nicam data. bit c4 indicates that the sound conveyed by the fm mono channel is identical to the sound signal conveyed by the nicam channel. the error byte contains the number of sound sample errors, resulting from parity checking, that occurred in the past 128 ms period. the bit error rate (ber) can be calculated using the following equation: ber bit errors total bits ----------------------- error byte 1.74 10 5 C ? =
1999 dec 20 12 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 6.1.8 nicam auto - mute this function is enabled by setting bit amute to logic 0 (see section 10.3.11). upper and lower error limits may be defined by writing appropriate values to two registers in the i 2 c-bus section (see sections 10.3.13 and 10.3.14). when the number of errors in a 128 ms period exceeds the upper error limit the auto-mute function will switch the output sound from nicam to whatever sound is on the first sound carrier (fm or am). when the error count is smaller than the lower error limit the nicam sound is restored. the auto-mute function can be disabled by setting bit amute to logic 1. in this condition clicks become audible when the error count increases; the user will hear a signal of degrading quality. a decision to enable/disable the auto-muting is taken by the microcontroller based on an interpretation of the application control bits c1, c2, c3 and c4 and, possibly, any additional strategy implemented by the set maker in the microcontroller software. for nicam l applications, it is recommended to demodulate am sound in the first sound if and connect the audio signal to the mono input of the tda9875a. by setting bit amsel (see section 10.3.11), the auto-mute function will switch to the audio adc instead of switching to the first sound carrier. the adc source selector (see section 10.3.20) should be set to mono input, where the am sound signal should be connected. 6.1.9 c rystal oscillator the circuitry of the crystal oscillator is fully integrated, only the external 24.576 mhz crystal is needed (see fig.10). 6.1.10 t est pins test pins test1 and test2 are active high and in the normal operating mode of the device they are connected to v ssd1 . test functions are for manufacturing tests only and are not available to customers. without external circuitry these pins are pulled down to a low level with internal resistors. 6.1.11 p ower fail detector the power fail detector monitors the internal power supply for the digital part of the device. if the supply has temporarily been lower than the specified lower limit, the power-on reset bit por (see section 10.4.1), will be set to logic 1. bit clrpor (see section 10.3.2) resets the power-on reset flip-flop to low. if this is detected, an initialization of the tda9875a has to be carried out to ensure reliable operation. 6.1.12 p ower - on reset the reset is active low. in order to perform a reset at power-up, a simple rc circuit may be used which consists of the integrated passive pull-up resistor and an external capacitor connected to ground. the pull-up resistor has a nominal value of 50 k w , which can easily be measured between pins creset and v ddd2 . before the supply voltage has reached a certain minimum, the state of the circuit is completely undefined, and it remains in this undefined state unless a reset is applied. the reset is guaranteed to be active when: the power supply is within the specified limits (4.75 and 5.5 v) the crystal oscillator is functioning the voltage at pin creset is below 0.3v ddd (1.5 v if v ddd = 5.0 v, typically below 1.8 v). the required capacitor value depends on the gradient of the rising power supply voltage. the time constant of the rc circuit should be clearly larger than the rise time of the power supply, to make sure that the reset condition is always satisfied (see fig.4), even considering the tolerance spread. to avoid problems with a too slow discharging of the capacitor at power-down, it may be helpful to add a diode from pin creset to v ddd . it should be noted that the internal esd protection diode does not help here as it only conducts at higher voltages. under difficult power supply conditions (e.g. very slow or non-monotonic ramp-up), it is recommended to drive the reset line from a microcontroller port or the like. handbook, halfpage mhb595 reset active guaranteed 1.5 5 voltage (v) t v creset < 0.3v ddd v ddd > 4.75 v fig.4 reset at power-on.
1999 dec 20 13 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 6.2 digital signal processing handbook, full pagewidth mgk108 2 from adc 2 2 2 2 level adjust level adjust digital crossbar select 2 level adjust level adjust and mute level adjust and mute level adjust level adjust level adjust 2 dc filter monitor select peak detection 2 nicam 2 2 2 2 2 16 2 fm 2 4 fixed de-emphasis matrix fixed de-emphasis 2 1 matrix 2 matrix 2 matrix 2 matrix volume soft-mute bass/treble beeper 2 i 2 s1 i 2 s2 dac i 2 c-bus matrix automatic volume level spatial pseudo volume bass/treble bass boost contour soft-mute beeper adaptive de-emphasis dc filter i 2 s1 i 2 s2 12 10 8 6 4 2 main auxiliary fig.5 dsp data flow diagram.
1999 dec 20 14 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 6.2.1 l evel scaling all input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range from +15 to - 15 db (see fig.5). it is recommended to scale all input channels to be 15 db below full-scale ( - 15 db full-scale) under nominal conditions. 6.2.2 nicam pat h the nicam path has a switchable j17 de-emphasis. 6.2.3 fm (am) pat h a high-pass filter suppresses dc offsets from the fm demodulator due to carrier frequency offsets and supplies the monitor/peak function with dc values and an unfiltered signal, e.g. for the purpose of carrier detection. the de-emphasis function offers fixed settings for the supported standards (50, 60 or 75 m s and j17). an adaptive de-emphasis is available for wegener-panda 1 encoded programs. a matrix performs the dematrixing of the a2 stereo, dual and mono signals. 6.2.4 nicam auto - mute if nicam b/g, i or d/k is received, the auto-mute is enabled and the signal quality becomes poor, the digital crossbar switch switches automatically to fm and switches the matrix to channel 1. the automatic switching depends on the nicam bit error rate. the auto-mute function can be disabled via the i 2 c-bus. for nicam l applications, it is recommended to demodulate am sound in the first sound if and connect the audio signal to the mono input of the tda9875a. by setting bit amsel (see section 10.3.11), the auto-mute function will switch to the audio adc instead of switching to the first sound carrier. the adc source selector bits (see section 10.3.20) should be set to mono input, where the am sound signal should be connected. 6.2.5 m onitor this function provides data words from a number of locations in the signal processing paths to the i 2 c-bus interface (2 data bytes). signal sources include the fm demodulator outputs, most inputs to the digital crossbar switch and the outputs of the adc. source selection and data read-out is performed via the i 2 c-bus. optionally, the peak value can be measured instead of simply taking samples. the internally stored peak value is reset to zero when the data is read via the i 2 c-bus. the monitor function may be used, for example, for signal level measurements or carrier detection. 6.2.6 l oudspeaker (m ain ) channel the matrix provides the following functions: forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. there are fixed coefficient sets for spatial settings of 30%, 40% and 52%. the automatic volume level (avl) function provides a constant output level of - 23 db (full-scale) for input levels between 0 and - 29 db (full-scale). there are some fixed decay time constants to choose from, i.e. 2, 4 and 8 s. pseudo stereo is based on a phase shift in one channel via a second-order all-pass filter. there are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 hz. volume is controlled individually for each channel ranging from +24 to - 83 db with 1 db resolution. there is also a mute position. for the purpose of a simple control software in the microcontroller, the decimal number that is sent as an i 2 c-bus data byte for volume control is identical to the volume setting in db (e.g. the i 2 c-bus data byte +10 sets the new volume value to +10 db). balance can be realized by independent control of the left and right channel volume settings. contour is adjustable between 0 and +18 db with 1 db resolution. this function is linked to the volume setting by means of microcontroller software. bass is adjustable between +15 and - 12 db with 1 db resolution and treble is adjustable between +12 and - 12 db with 1 db resolution. for the purpose of a simple control software in the microcontroller, the decimal number that is sent as an i 2 c-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in db (e.g. the i 2 c-bus data byte +8 sets the new value to +8 db). extra bass boost is provided up to 20 db with 2 db resolution. the implemented coefficient set serves merely as an example on how to use this filter. the beeper provides tones in a range from approximately 400 hz to 30 khz. the frequency can be selected via the i 2 c-bus. the beeper output signal is added to the loudspeaker and headphone channel signals.
1999 dec 20 15 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a the beeper volume is adjustable with respect to full-scale between 0 and - 93 db with 3 db resolution. the beeper is not effected by mute. soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. a smooth fading is achieved by a cosine masking. 6.2.7 h eadphone (a uxiliary ) channel the matrix provides the following functions: forced mono, stereo, channel swap, channel 1 and channel 2 (or c and s in dolby surround pro logic mode). volume is controlled individually for each channel in a range from +24 to - 83 db with 1 db resolution. there is also a mute position. for the purpose of a simple control software in the microcontroller, the decimal number that is sent as an i 2 c-bus data byte for volume control is identical to the volume setting in db (e.g. the i 2 c-bus data byte +10 sets the new volume value to +10 db). balance can be realized by independent control of the left and right channel volume settings. bass is adjustable between +15 and - 12 db with 1 db resolution and treble is adjustable between +12 and - 12 db with 1 db resolution. for the purpose of a simple control software in the microcontroller, the decimal number that is sent as an i 2 c-bus data byte for bass or treble is identical to the new bass or treble setting in db (e.g. the i 2 c-bus data byte +8 sets the new value to +8 db). the beeper provides tones in a range from approximately 400 hz to 30 khz. the frequency can be selected via the i 2 c-bus. the beeper output signal is added to the loudspeaker and headphone channel signals. the beeper volume is adjustable with respect to full-scale between 0 and - 93 db with 3 db resolution. the beeper is not effected by mute. soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. a smooth fading is achieved by a cosine masking. 6.2.8 f eature interface the feature interface comprises two i 2 s-bus input/output ports and a system clock output. each i 2 s-bus port is equipped with level adjust facilities that can change the signal level in a range from +15 to - 15 db with 1 db resolution. outputs can be disabled to improve emc performance. the i 2 s-bus output matrix provides the following functions: forced mono, stereo, channel swap, channel 1 and channel 2. one example of how the feature interface can be used in a tv set is to connect an external dolby surround pro logic dsp, such as the saa7710, to the i 2 s-bus ports. outputs must be enabled and a suitable master clock signal for the dsp can be taken from pin sysclk. a stereo signal from any source will be output on one of the i 2 s-bus serial data outputs and the four processed signal channels will be entered at both i 2 s-bus serial data inputs. left and right could then be output to the power amplifiers via the main channel, centre and surround via the auxiliary channel. 6.2.9 c hannel from the audio adc the signal level at the output of the adc can be adjusted in a range from +15 to - 15 db with 1 db resolution. the audio adc itself is scaled to a gain of - 6 db. 6.2.10 c hannel to the analog crossbar path level adjust with control positions 0, +3, +6 and +9 db. 6.2.11 d igital crossbar switch input channels to the crossbar switch are from the audio adc, i 2 s1, i 2 s2, fm path, nicam path and from the loudspeaker channel path after matrix and avl (see fig.8). output channels comprise loudspeaker, headphone, i 2 s1, i 2 s2 and audio dacs for line output and scart. i 2 s1 and i 2 s2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals. 6.2.12 s ignal gain there are a number of functions that can provide signal gain, e.g. volume, bass and treble control. great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. the nominal signal level of the various signal sources to the digital crossbar switch should be 15 db below digital full-scale ( - 15 db full-scale). this means that a volume setting of, say, +15 db would just produce a full-scale output signal and not cause clipping, if the signal level is nominal. sending illegal data patterns via the i 2 c-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions.
1999 dec 20 16 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 6.2.13 e xpert mode the tda9875a provides a special expert mode that gives direct write access to the internal coefficient ram (cram) of the dsp. it can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. however, this mode must be used with great care. more information on the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be made available on request. 6.2.14 dsp functions table 5 overview of dsp functions function expert mode parameter value unit bass control for loudspeaker and headphone output yes control range - 12 to +15 db resolution 1 db resolution at frequency 40 hz treble control for loudspeaker and headphone output yes control range - 12 to +12 db resolution 1 db resolution at frequency 14 khz contour for loudspeaker output yes control range 0 to +18 db resolution 1 db resolution at frequency 40 hz bass boost for loudspeaker output yes control range 0 to +20 db resolution 2 db resolution at frequency 20 hz corner frequency 350 hz volume control for each separate channel in loudspeaker and headphone output no control range - 83 to +24 db resolution 1 db mute position at step 1010 1100 soft mute for loudspeaker and headphone output no processing time 32 ms spatial effects yes anti-phase crosstalk positions 30, 40 and 52 % pseudo stereo yes 90 degrees phase shift at frequency 150, 200 and 300 hz beeper additional to the signal in the loudspeaker and headphone channel yes beep frequencies see section 10.3.38 control range 0 to - 93 db resolution 3 db mute position at step 0010 0000 automatic volume level (avl) yes step width quasi continuously avl output level for an input level between 0 and - 29 db (full-scale) - 23 db attack time 10 ms decay time constant 2, 4 and 8 s
1999 dec 20 17 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 6.3 analog audio section general no - 3 db lower corner frequency of dsp 10 hz - 1 db bandwidth of dsp 14.5 khz level adjust i 2 s1 and i 2 s2 inputs yes control range - 15 to +15 db resolution 1 db level adjust i 2 s1 and i 2 s2 outputs yes control range - 15 to +15 db resolution 1 db mute position at step 0001 0000 level adjust analog crossbar path no control positions 0, 3, 6 and 9 db level adjust audio adc outputs yes control range +15 to - 15 db resolution 1 db level adjust nicam path yes control range +15 to - 15 db resolution 1 db level adjust fm path yes control range +15 to - 15 db resolution 1 db function expert mode parameter value unit handbook, full pagewidth mgk109 - 3 db 2 scart 1 2 2 2 2 2 2 2 2 scart 1 scart 2 line output 2 2 main auxiliary 2 2 2 2 2 - 3 db 2 scart 2 2 external mono 2 analog crossbar switch analog matrix analog matrix analog matrix 2 2 2 2 2 2 nicam i 2 s1 i 2 s1 fm i 2 s2 i 2 s2 2 d a 2 d a 2 d a a d 3 db 0 db 3 db 0 db 3 db 0 db dsp and digital crossbar switch fig.6 block diagram for the audio section.
1999 dec 20 18 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 6.3.1 a nalog crossbar switch and analog matrix there are a number of analog input and output ports with the tda9875a (see figs 6 and 8). analog source selector switches are employed to provide the desired analog signal routing capability. the analog signal routing is performed by the analog crossbar switch section. a dual audio adc provides the connection to the dsp section and a dual audio dac provides the connection from the dsp section to the analog crossbar switch. the digital signal routing is performed by a digital crossbar switch. the basic signal routing philosophy of the tda9875a is that each switch handles two signal channels at the same time, e.g. left and right, language a and b, directly at the source. each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a signal from one input channel, say language a, to both output channels or for swapping left and right channels (see fig.7). the analog matrix provides the functions given in table 6. table 6 analog matrix functions all switches and matrices are controlled via the i 2 c-bus. 6.3.2 scart inputs the scart specification allows for a signal level of up to 2 v (rms). because of signal handling limitations, due to the 5 v supply voltage of the tda9875a, it is necessary to have fixed 3 db attenuators at the scart inputs to obtain a 2 v input. this results in a - 3 db scart-to-scart copy gain. if 0 db copy gain is preferred (with a maximum input of 1.4 v), there are 0/3 db amplifiers at the outputs of scart 1 and scart 2 and at the line output. the input attenuator is realized by an external series resistor in combination with the input impedance, both of which form a voltage divider. with this voltage divider the maximum scart signal level of 2 v (rms) is scaled down to 1.4 v (rms) at the input pin. 6.3.3 e xternal and mono inputs the 3 db input attenuators are not required for the external and mono inputs, because those signal levels are under control of the tv designer. the maximum allowed input level is 1.4 v (rms). by adding external series resistors, the external inputs can be used as an additional scart input. 6.3.4 scart outputs the scart outputs employ amplifiers with two gain settings. the gain can be set to 3 or 0 db via the i 2 c-bus. the 3 db position is needed to compensate for the 3 db attenuation at the scart inputs should scart-to-scart copies with 0 db gain be preferred [under the condition of 1.4 v (rms) maximum input level]. the 0 db position is needed, for example, for an external-to-scart copy with 0 db gain. mode matrix output left output right output 1 left input right input 2 right input left input 3 left input left input 4 right input right input handbook, halfpage mgk110 analog matrix left input right input left output right output fig.7 analog matrix.
1999 dec 20 19 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 6.3.5 l ine output the line output can provide an unprocessed copy of the audio signal in the loudspeaker channels. this can be either an external signal that comes from the dual audio adc, or a signal from an internal digital audio source that comes from the dual audio dac. the line output employs amplifiers with two gain settings. the 3 db position is needed to compensate for the attenuation at the scart inputs, while the 0 db position is needed, for example, for non-attenuated external or internal digital signals (see section 6.3.4). 6.3.6 l oudspeaker (m ain ) and headphone (a uxiliary ) outputs signals from any audio source can be applied to the loudspeaker and to the headphone output channels via the digital crossbar switch and the dsp. 6.3.7 d ual audio dac the tda9875a contains three dual audio dacs, one for the connection from the dsp to the analog crossbar switch section and two for the loudspeaker and headphone outputs. each of the three dual low-noise high-dynamic range dacs consists of two 15-bit dacs with current outputs, followed by a buffer operational amplifier. the audio dacs operate with four-fold oversampling and noise shaping. 6.3.8 d ual audio adc there is one dual audio adc in the tda9875a for the connection of the analog crossbar switch section to the dsp. the dual audio adc consists of two bitstream third-order sigma-delta audio adcs and a high-order decimation filter. 6.3.9 s tandby mode the standby mode, selected by setting bit stdby to logic 1 (see section 10.3.2) disables most functions and reduces power dissipation. the analog crossbar switch and the scart section remain operational and can be controlled by the i 2 c-bus to support copying of analog signals from scart-to-scart. unused internal registers may lose their information in the standby mode. therefore, the device needs to be initialized on returning to the normal operating mode. this can be accomplished in the same way as after a power-on reset. 6.3.10 s upply ground the different supply grounds v ss are internally connected via the substrate. it is recommended to connect all ground pins by means of a copper plane close to the pins.
1999 dec 20 20 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mhb600 scart 1 scart 2 fm/am part external adc - 6 db mono fm level adjust adc level adjust dac i 2 s2 output level adjust dac gain dac main auxiliary line scart 1 scart 2 i 2 s1 i 2 s2 dac digital matrix digital matrix buffer 0/ + 3 db buffer 0/ + 3 db buffer 0/ + 3 db analog matrix analog matrix analog matrix i 2 s1 output level adjust digital matrix digital matrix digital matrix automatic volume level loudspeaker channel processing headphone channel processing stereo decoder fixed de-emphasis adaptive de-emphasis fm/am demodulator nicam part nicam level adjust nicam decoder de-emphasis i 2 s1 input level adjust i 2 s2 input level adjust i 2 s1 i 2 s2 fig.8 audio signal flow diagram.
1999 dec 20 21 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 7 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model: c = 100 pf; r = 1.5 k w . 2. machine model: c = 200 pf; l = 0.75 m h; r = 0 w . 8 thermal characteristics symbol parameter conditions min. max. unit v dd dc supply voltage - 0.5 +6.0 v d v dd voltage differences between two v dd pins - 550 mv v n voltage on any other pin - 0.5 v dd + 0.5 v i ddd , i ssd dc current per digital supply pin - 180 ma i lu(prot) latch-up protection current 100 - ma p tot total power dissipation - 1.0 w t stg storage temperature - 55 +125 c t amb ambient temperature - 20 +70 c v es electrostatic handling voltage note 1 - 2000 +2000 v note 2 - 200 +200 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air tda9875a (sdip64) 40 k/w tda9875ah (qfp64) 50 k/w
1999 dec 20 22 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 9 characteristics v sif(p-p) = 300 mv; agcoff = 0; agcslow = 0; agclev = 0; level and gain settings in accordance with note 1; v dd =5v; t amb =25 c; settings in accordance with b/g standard; fm deviation 50 khz; f mod = 1 khz; fm sound parameters in accordance with system a2; nicam in accordance with ebu speci?cation ; 1 k w measurement source resistance for af inputs; with external components of fig.10; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd1 digital supply voltage 1 4.75 5.0 5.5 v v ssd1 digital supply ground 1 note 2 - 0.0 - v i ddd1 digital supply current 1 v ddd1 =5.0v 5873 88ma v ddd2 digital supply voltage 2 4.75 5.0 5.5 v v ssd2 digital supply ground 2 note 2 - 0.0 - v i ddd2 digital supply current 2 v ddd2 = 5.0 v; system clock output disabled 0.1 0.4 2 ma v ssd3 digital supply ground 3 note 2 - 0.0 - v v ssd4 digital supply ground 4 note 2 - 0.0 - v v dda analog supply voltage 4.75 5.0 5.5 v i dda analog supply current for dac part v dda = 5.0 v; digital silence 44 56 68 ma v ssa1 analog ground for analog front-end note 2 - 0.0 - v v ssa2 analog ground for audio adc part note 2 - 0.0 - v v ssa3 analog ground for audio dac part note 2 - 0.0 - v v ssa4 analog ground for scart - 0.0 - v demodulator supply decoupling and references v dec1 analog supply decoupling voltage for demodulator part 3.0 3.3 3.6 v v ref1 analog reference voltage for demodulator part - 2 - v i ref1(sink) sink current at pin v ref1 - 200 -m a audio supply decoupling and references v dec2 analog supply decoupling voltage for audio adc part 3.0 3.3 3.6 v v ref2 reference voltage ratio for audio adcs referenced to v dec2 and v ssa2 - 50 - % z vref2-vdec2 impedance pins v ref2 to v dec2 - 20 - k w z vref2-vssa2 impedance pins v ref2 to v ssa2 - 20 - k w v ref3 reference voltage ratio for audio dac and operational ampli?er referenced to v dda and v ssa3 - 50 - % z vref3-vdda impedance pins v ref3 to v dda - 20 - k w z vref3-vssa3 impedance pins v ref3 to v ssa3 - 20 - k w
1999 dec 20 23 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a power fail detector v th(pf) power fail threshold voltage - 3.9 - v digital inputs and outputs i nputs cmos level input, pull-down (pins test1 and test2) v il low-level input voltage -- 0.3v ddd v v ih high-level input voltage 0.7v ddd -- v c i input capacitance -- 10 pf z i input impedance - 50 - k w cmos level input, hysteresis, pull-up (pin creset) v il low-level input voltage -- 0.3v ddd v v ih high-level input voltage 0.7v ddd -- v v hys hysteresis voltage - 1.3 - v c i input capacitance -- 10 pf z i input impedance 30 50 - k w i nputs / outputs i 2 c-bus level input with schmitt trigger, open-drain output stage, 400 khz i 2 c-bus operation (pins scl and sda) v il low-level input voltage -- 0.3v ddd v v ih high-level input voltage 0.7v ddd -- v v hys hysteresis voltage - 0.05v ddd - v i li input leakage current -- 10 m a c i input capacitance -- 10 pf v ol low-level output voltage -- 0.6 v c l load capacitance -- 400 pf ttl/cmos level, 4 ma 3-state output stage, pull-up (pins pclk, nicam, addr1, addr2, p1, p2, sck, ws, sdo1, sdo2, sdi1 and sdi2) v il low-level input voltage -- 0.8 v v ih high-level input voltage 2.0 -- v c i input capacitance -- 10 pf v ol low-level output voltage -- 0.4 v v oh high-level output voltage 2.4 -- v c l load capacitance -- 100 pf z i input impedance - 50 - k w o utputs cmos level output, 4 ma 3-state output stage, slew rate controlled (pin sysclk) v ol low-level output voltage -- 0.3v ddd v v oh high-level output voltage 0.7v ddd -- v c l load capacitance -- 100 pf i liz 3-state leakage current v i = 0 to v ddd -- 10 m a symbol parameter conditions min. typ. max. unit
1999 dec 20 24 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a sif1 and sif2 analog inputs v sif(max)(p-p) maximum composite sif input voltage for clipping (peak-to-peak value) sif input level adjust 0 db - 941 - mv sif input level adjust - 10 db - 2976 - mv v sif(min)(p-p) minimum composite sif input voltage for lower limit of agc (peak-to-peak value) sif input level adjust 0 db - 59 - mv sif input level adjust - 10 db - 188 - mv agc agc range - 24 - db f i input frequency 4 - 9.2 mhz r i input resistance agclev = 0 10 -- k w c i input capacitance - 7.5 11 pf d f fm fm deviation b/g standard; thd < 1% 100 -- khz d f fm(fs) fm deviation full-scale level terrestrial fm; level adjust 0 db 150 -- khz c/n fm fm carrier-to-noise ratio n fm bandwidth = 6 mhz; white noise for s/n = 40 db; ccir468 ; quasi peak - 77 - c/n n nicam carrier-to-noise ratio n n bandwidth = 6 mhz; bit error rate = 10 - 3 ; white noise - 66 - a ct crosstalk attenuation sif1 to sif2 f i = 4 to 9.2 mhz; note 3 50 -- db demodulator performance thd + n total harmonic distortion plus noise from fm source to any output; v o = 1 v (rms) with low-pass ?lter - 0.3 0.5 % from nicam source to any output; v o = 1 v (rms) with low-pass ?lter - 0.1 0.3 % s/n signal-to-noise ratio sc1 from fm source to any output; v o = 1 v (rms); ccir468 ; quasi peak 64 70 - db sc2 from fm source to any output; v o = 1 v (rms); ccir468 ; quasi peak 60 66 - db nicam source; v o = 1 v (rms); note 4 -- - b - 3db - 3 db bandwidth from fm source to any output 14.5 15 - khz from nicam source to any output 14.5 15 - khz f res frequency response 20 hz to 14 khz from fm or nicam to any output; f ref = 1 khz; inclusive pre-emphasis and de-emphasis - 2 - db symbol parameter conditions min. typ. max. unit db hz ------ - db hz ------ -
1999 dec 20 25 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a a cs(dual) dual signal channel separation note 5 65 70 - db a cs(stereo) stereo channel separation note 6 40 45 - db a am am suppression for fm am: 1 khz, 30% modulation; reference: 1 khz, 50 khz deviation 50 -- db s/n am am demodulation sif level 100 mv (rms); 54% am; 1 khz af; ccir468 ; quasi peak 36 45 - db i dentification for fm systems mod p pilot modulation for identi?cation 25 50 75 % c/n p pilot sideband carrier-to-noise ratio for identi?cation start - 27 - f ident identi?cation window b/g stereo slow mode 116.85 - 118.12 hz medium mode 116.11 - 118.89 hz fast mode 114.65 - 120.46 hz b/g dual slow mode 273.44 - 274.81 hz medium mode 272.07 - 276.20 hz fast mode 270.73 - 277.60 hz t ident(on) total identi?cation time on slow mode -- 2s medium mode -- 1s fast mode -- 0.5 s t ident(off) total identi?cation time off slow mode -- 2s medium mode -- 1s fast mode -- 0.5 s analog audio inputs m ono input and external input v i(nom)(rms) nominal level input voltage (rms value) - 500 - mv v i(clip)(rms) clipping level input voltage (rms value) thd < 3%; note 7 1250 1400 - mv r i input resistance note 7 28 35 42 k w scart inputs v i(nom)(rms) nominal level input voltage at input pin (rms value) - 3 db divider with external 15 k w resistor; note 8 - 350 - mv v i(clip)(rms) clipping level input voltage at input pin (rms value) - 3 db divider with external 15 k w resistor; thd < 3%; notes 7 and 8 1250 1400 - mv r i input resistance note 7 28 35 42 k w symbol parameter conditions min. typ. max. unit db hz ------ -
1999 dec 20 26 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a analog audio outputs l oudspeaker (m ain ) and headphone (a uxiliary ) outputs v o(clip)(rms) clipping level output voltage (rms value) thd < 3% 1250 1400 - mv r o output resistance 150 250 375 w r l(ac) ac load resistance 10 -- k w r l(dc) dc load resistance 10 -- k w c l load capacitance - 10 12 nf v offset(dc) static dc offset voltage - 30 70 mv a mute mute suppression nominal input signal from any source; f i = 1 khz 80 -- db g ro(main,aux) roll-off gain at 14.5 khz for main and auxiliary channels from any source - 3 - 2 - db psrr main,aux power supply ripple rejection for main and auxiliary channels f ripple = 70 hz; v ripple = 100 mv (peak); c vref =47 m f; signal from i 2 s-bus 40 45 - db scart outputs and line output v o(nom)(rms) nominal level output voltage (rms value) 3 db ampli?cation - 500 - mv v o(clip)(rms) clipping level output voltage (rms value) thd < 3% 1250 1400 - mv r o output resistance 150 250 375 w r l(ac) ac load resistance 10 -- k w r l(dc) dc load resistance 10 -- k w c l load capacitance -- 2.5 nf v offset(dc) static dc offset voltage output ampli?ers at 3 db position - 30 50 mv a mute mute suppression nominal input signal from any source; f i = 1 khz 80 -- db b bandwidth from scart, external and mono sources; - 3 db bandwidth 20 -- khz from dsp sources; - 3 db bandwidth 14.5 -- khz psrr power supply ripple rejection f ripple = 70 hz; v ripple = 100 mv (peak); c vref =47 m f; signal from i 2 s-bus 40 45 - db symbol parameter conditions min. typ. max. unit
1999 dec 20 27 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a audio performance thd + n total harmonic distortion plus noise v i =v o = 1 v (rms); f i = 1 khz; bandwidth 20 hz to 15 khz; note 9 from any analog audio input to i 2 s-bus - 0.1 0.3 % from i 2 s-bus to any analog audio output - 0.1 0.3 % scart-to-scart copy - 0.1 0.3 % scart-to-main copy - 0.2 0.5 % s/n signal-to-noise ratio reference voltage v o = 1.4 v (rms); f i = 1 khz; ccir468 ; quasi peak; note 9 from any analog audio input to i 2 s-bus 73 77 - db from i 2 s-bus to any analog audio output 78 85 - db scart-to-scart copy 78 85 - db scart-to-main copy 73 77 - db a ct crosstalk attenuation between any analog input pairs; f i = 1 khz 70 -- db between any analog output pairs; f i =10khz 65 -- db a cs channel separation between left and right of any input pair 65 -- db between left and right of any output pair 60 -- db g a gain from scart-to-scart with - 3 db input voltage divider output ampli?er in 3 db position; r ext =15k w 10% - 1.5 0 +1.1 db output ampli?er in 0 db position; r ext =15k w 10% - 4.5 - 3.0 - 1.9 db crystal speci?cation (fundamental mode) f xtal crystal frequency - 24.576 - mhz c l load capacitance - 20 - pf c 1 series capacitance - 20 - ff c 0 parallel capacitance -- 7pf f pull pulling sensitivity c l changed from 18 to 16 pf - 25 - r r equivalent series resistance at nominal frequency -- 30 w r n equivalent series resistance of unwanted mode 2r r --w d t temperature range - 20 +25 +70 c symbol parameter conditions min. typ. max. unit 10 6 C pf -----------
1999 dec 20 28 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a notes 1. definitions of levels and level setting: a) the full-scale level for analog audio signals is 1.4 v (rms). b) the nominal level at the digital crossbar switch is defined at - 15 db (full-scale). c) nominal audio input levels for external and mono: 500 mv (rms) at - 9 db (full-scale). d) see also tables 7 and 8. 2. all analog and digital supply ground pins are connected internally. 3. set demodulator to am mode. apply an am carrier (with 1 khz and 100%) to one channel. check agc step. switch agc off and set agc to the gain step found. measure the 1 khz signal level of this channel and take it as a reference. switch to the other sif input to which no signal is connected and which is terminated with 50 w . now measure the 1 khz crosstalk signal level. the sif source resistance should be low (50 w ). 4. nicam in accordance with ebu specification . audio performance is limited by the dynamic range of the nicam728 system. due to compansion, the quantization noise is never lower than - 62 db (unweighted rms) with respect to the input level. 5. fm source; in dual mode only a (respectively b) signal modulated; measured at b (respectively a) channel output; v o = 1 v (rms) of modulated channel. 6. fm source; in stereo mode only l (respectively r) signal modulated; measured at r (respectively l) channel output; v o = 1 v (rms) of modulated channel. the stereo channel separation may be limited by adjustment tolerances of the transmitter. 7. if the supply voltage for the tda9875a is switched off, because of the esd protection circuitry, all audio input pins are short-circuited. to avoid a short-circuit at the scart inputs a 15 k w resistor ( - 3 db divider) has to be used. 8. the scart specification allows a signal level of up to 2 v (rms). because of signal handling limitations due to the 5 v supply voltage for the tda9875a, there is a need for fixed 3 db attenuators at the scart inputs. to achieve scart-to-scart copies with 0 db gain, there are 3 db/0 db amplifiers at the outputs of scart 1 and scart 2 and at the line output. the attenuator is realized by an internal resistor that works together with an external series resistor as a voltage divider. with this voltage divider the maximum scart input signal level of 2 v (rms) is scaled down to 1.4 v (rms) at the input pin. to avoid clipping, the 3 db gain must not be used if the scart input signal is larger than 1.4 v (rms). 9. adc level adjust is 6 db, all other level adjusts are 0 db. if an external - 3 db divider is used set output buffer gain to 3 db, tone control to 0 db, avl off and volume control to 0 db. x j adjustment tolerance -- 30 10 - 6 x d drift across temperature range -- 30 10 - 6 x a ageing -- 5 symbol parameter conditions min. typ. max. unit 10 6 C year -----------
1999 dec 20 29 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 7 level setting fm, am and nicam at 0 db (full-scale) = 1.4 v (rms); note 1 notes 1. nominal level at digital crossbar is defined at - 15 db (full-scale). dac gain setting 6 db. output buffer setting 0 db. nominal scart output level 500 mv (rms). 2. for stereo signals the output level is 6 db lower. the level adjust has to be increased by 6 db. standard mode transmitter nominal modulation depth nominal level at demodulator output carrier frequency mode ident de-emphasis fm/nicam level adjust m 2 channel 15 khz deviation - 24 db (full-scale); note 2 1 4.5 mhz fm - 75 m s+9db 2 4.724 mhz fm on 75 m s+9db b/g 2 channel 27 khz deviation - 19 db (full-scale) 1 5.5 mhz fm - 50 m s+4db 2 5.742 mhz fm on 50 m s+4db nicam - 11.2 db (full-scale) - 18 db (full-scale) 1 5.5 mhz fm - 50 m s+4db 2 5.85 mhz nicam off j17 +3 db i nicam - 15.8 db (full-scale) - 23 db (full-scale) 1 6.0 mhz fm - 50 m s+4db 2 6.552 mhz nicam off j17 +8 db d/k 2 channel 27 khz deviation - 19 db (full-scale) 1 6.5 mhz fm - 50 m s+4db 2 6.742 mhz fm on 50 m s+4db 2 channel 27 khz deviation - 19 db (full-scale) 1 6.5 mhz fm - 50 m s+4db 2 6.25 mhz fm on 50 m s+4db 2 channel 27 khz deviation - 19 db (full-scale) 1 6.5 mhz fm - 50 m s+4db 2 5.742 mhz fm on 50 m s+4db nicam - 11.2 db (full-scale) - 18 db (full-scale) 1 6.5 mhz fm - 50 m s+4db 2 5.85 mhz nicam off j17 +3 db l/l accent nicam 54% am - 19 db (full-scale) 1 6.5 mhz am - 50 m s+5db 2 5.85 mhz nicam off j17 +3 db
1999 dec 20 30 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... table 8 level setting sat fm at 0 db (full-scale) = 1.4 v (rms) source transmitter maximum modulation depth nominal level at demodulator output fm level adjust setting maximum level at crossbar dac gain setting output buffer nominal scart output voltage sat fm, stereo 50 khz deviation - 13 db (full-scale) +4 db - 9 db (full-scale) +6 db 0 db 1 v (rms) sat fm, mono 85 khz deviation - 9 db (full-scale) 0 db
1999 dec 20 31 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10 i 2 c-bus control 10.1 introduction the tda9875a is fully controlled via the i 2 c-bus. control is exercised by writing data to one or more internal registers. status information can be read from an array of registers to enable the controlling microcontroller to determine whether any action is required. the device has an i 2 c-bus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of 400 kbits/s. information concerning the i 2 c-bus can be found in brochure i 2 c-bus and how to use it (order number 9398 393 40011). to avoid conflicts in a real application with other ics providing similar or complementary functions, there are four possible slave addresses available which can be selected by pins addr1 and addr2 (see table 9). table 9 possible slave addresses the i 2 c-bus interface remains operational in the standby mode of the tda9875a to allow control of the analog source selectors with regard to scart-to-scart copying. the device will not respond to a general call on the i 2 c-bus, i.e. when a slave address of 0000000 is sent by a master. the data transmission between the microcontroller and the other i 2 c-bus controlled ics is not disturbed when the supply voltage of the tda9875a is not connected. 10.2 power-up state at power-up the device is in the following state: all outputs muted no sound carrier frequency loaded general-purpose i/o pins ready for input (high) input sif1 selected with: C agc on C small hysteresis C sif input level shift 0 db. demodulators for both sound carriers set to fm with: C identification for b/g and d/k, response time 1 s C level adjust set to 0 db C de-emphasis 50 m s C matrix set to mono. main channel set to fm input with: C spatial off C pseudo off C avl off C volume mute C bass flat C treble flat C contour off C bass boost flat. auxiliary channel set to fm input with: C volume mute C bass flat C treble flat. feature interface all outputs off beeper off monitoring of carrier 1 fm demodulator dc output. after power-up a device initialization has to be performed via the i 2 c-bus to put the tda9875a into the proper mode of operation, in accordance with the desired tv standard, audio control settings, etc. addr2 addr1 slave address a6 a5 a4 a3 a2 a1 a0 low low 1011000 low high 1011001 high low 1011010 high high 1011011
1999 dec 20 32 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3 slave receiver mode as a slave receiver, the tda9875a provides 46 registers for storing commands and data. these registers are accessed via so-called subaddresses. a subaddress can be thought of as a pointer to an internal memory location. table 10 i 2 c-bus; slave address, subaddress and data format table 11 explanation of table 10 it is allowed to send more than one data byte per transmission to the tda9875a. in this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at subaddress. a transmission can start at any valid subaddress. each byte is acknowledged with ack (acknowledge). there is no wrap-around of subaddresses. commands and data are processed as soon as they have been completely received. functions requiring more than one byte will, thus, be executed only after all bytes for that function have been received. if the transmission is terminated (stop condition) before all bytes have been received, the incomplete data for that function are ignored. table 12 format for a transmission employing auto-increment of subaddresses note 1. n data bytes with auto-increment of subaddresses. data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the functions of volume, bass, treble control, bass boost and level adjust. detection of a stop condition without a preceding acknowledge bit is regarded as a bus error. the last operation will then not be executed. s slave address 0 ack subaddress ack data ack p bit function s start condition slave address 7-bit device address 0 data direction bit (write to device) ack acknowledge by slave subaddress address of register to write to data data byte to be written into register p stop condition s slave address 0 ack subaddress ack data byte a (1) data ac k p
1999 dec 20 33 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 13 overview of the slave receiver registers subaddress (decimal) data function msb lsb 0 00sgggggagc level shift, agc gain selection 1 cccccccc general con?guration 2 p 0 0 m m s s s monitor select, peak detector on/off 3 ffffffff carrier 1 frequency; most signi?cant part 4 ffffffff carrier 1 frequency 5 ffffffff carrier 1 frequency; least signi?cant part 6 ffffffff carrier 2 frequency; most signi?cant part 7 ffffffff carrier 2 frequency 8 ffffffff carrier 2 frequency; least signi?cant part 9 cccccccc demodulator con?guration 10 ddddddddfm de-emphasis 11 00000mmmfm matrix 12 000lllll channel 1 output level adjust 13 000lllll channel 2 output level adjust 14 t t 0 c 0 c c c nicam con?guration 15 000lllll nicam output level adjust 16 llllllll nicam lower error limit 17 uuuuuuuu nicam upper error limit 18 mmmmmmmm audio mute control 19 g m m m g s s s dac output select 20 0 g m m 0 s s s scart 1 output select 21 0 g m m 0 s s s scart 2 output select 22 0 g m m 0 0 0 s line output select 23 ssslllll adc output select 24 0 m m m 0 s s s main channel select 25 00ssppaa audio effects (avl, pseudo and spatial) 26 vvvvvvvvv olume control, main left 27 vvvvvvvvv olume control, main right 28 000ccccc contour control, main 29 000bbbbb bass control, main 30 000ttttt treble control, main 31 0 m m m 0 s s s auxiliary channel select 32 vvvvvvvvv olume control, auxiliary left 33 vvvvvvvvv olume control, auxiliary right 34 000bbbbb bass control, auxiliary 35 000ttttt treble control, auxiliary 36 000cccccf eature interface con?guration 37 0 mmm 0 s s si 2 s1 output select
1999 dec 20 34 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a the following sub-sections provide a detailed description of the slave receiver registers. 10.3.1 agc gain register if the automatic gain control function is switched off in the general configuration register, the contents of this register will define a fixed gain of the agc stage. the input voltages given are meant to generate a full-scale output from the sif adc. if automatic gain control is on, the agcgain setting is ignored. after switching off the automatic gain control function, the latest gain control setting is copied to the agc gain register. if the agc input level shift bit agclev is set to logic 1 the input signal is scaled with - 10 db. the agclev bit is also active if the automatic gain function is enabled. it should be noted that the input voltages should be considered as approximate target values. table 14 subaddress 0 (note 1) note 1. the default setting at power-up is 0000 0000. 38 000iiiiii 2 s1 input level adjust 39 000oooooi 2 s1 output level adjust 40 0 mmm 0 s s si 2 s2 output select 41 000iiiiii 2 s2 input level adjust 42 000oooooi 2 s2 output level adjust 43 00000 f f f beeper frequency 44 00vvvvvv beeper volume, main and auxiliary 45 bbbbbbbb bass boost, main left and right bit name value description 7 (msb) b7 0 set to logic 0 6 b6 0 set to logic 0 5 agclev 1 input signal scaled with - 10 db 0 input signal not scaled 4 agcgain - gain control bits (see table 15) 3 2 1 0 (lsb) subaddress (decimal) data function msb lsb
1999 dec 20 35 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 15 gain control bits note 1. the default setting at power-up is 0000 0000. msb lsb agc gain (db) sif input voltage [mv (p-p)] b7 b6 b5 b4 b3 b2 b1 b0 000/111111 0.0 941/2976 000/111110 0.8 861/2723 000/111101 1.5 788/2490 000/111100 2.3 720/2278 000/111011 3.1 659/2084 000/111010 3.9 603/1906 000/111001 4.6 551/1744 000/111000 5.4 504/1595 000/110111 6.2 461/1459 000/110110 7.0 422/1334 000/110101 7.7 386/1221 000/110100 8.5 353/1117 000/110011 9.3 323/1021 000/110010 10.1 295/934 000/110001 10.8 270/855 000/110000 11.6 247/782 000/101111 12.4 226/715 000/101110 13.2 207/654 000/101101 13.9 189/598 000/101100 14.7 173/547 000/101011 15.5 158/501 000/101010 16.3 145/458 000/101001 17.0 132/419 000/101000 17.8 121/383 000/100111 18.6 111/350 000/100110 19.4 101/321 000/100101 20.1 93/293 000/100100 20.9 85/268 000/100011 21.7 78/245 000/100010 22.5 71/224 000/100001 23.2 65/205 000/100000 24.0 59/188 (note 1)
1999 dec 20 36 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.2 g eneral configuration register table 16 subaddress 1 (note 1) note 1. the default setting at power-up is 1100 0000. bit name value description 7 (msb) p2out - this bit controls the general purpose input/output pin p2. the contents of this bit is written directly to the corresponding pin. if input is desired, the bit must be set to logic 1 to allow the pin to be pulled low externally. input from the pin is re?ected in the device status register (see section 10.4.1). 6 p1out - this bit controls the general purpose input/output pin p1. the contents of this bit is written directly to the corresponding pin. if input is desired, the bit must be set to logic 1 to allow the pin to be pulled low externally. input from the pin is re?ected in the device status register (see section 10.4.1). p1out is recommended to be used for switching an sif trap for the adjacent picture carrier in designs that employ such a trap. 5 stdby 1 the ic is in the standby mode. most functions are disabled and power dissipation is somewhat reduced, but the analog selectors/matrices remain operational to support analog copying from scart-to-scart. 0 the ic is in the normal operating mode. on return from standby mode, the device is in its power-on reset mode and needs to be re-initialized. 4 init 1 causes initialization of the tda9875a to its default settings. this has the same effect as a power-on reset. if there is a con?ict between the default settings and any bit set to logic 1 in this register, the bits of this register have priority over the corresponding default setting. 0 automatically reset to logic 0 after initialization. when set to logic 0, the tda9875a is in its normal operating mode. 3 clrpor 1 resets the power fail detector to low. 0 this bit is automatically reset to logic 0 after bit por in the device status register has been reset. 2 agcslow 1 a longer decay time is selected for input signals with strong video modulation (intercarrier). this bit only has an effect when bit agcoff = 0. 0 selects normal attack and decay times for the agc. 1 agcoff 1 forces the agc block to a ?xed gain as de?ned in the agc gain register. 0 the automatic gain control function is enabled and the contents of the agc gain register is ignored. 0 (lsb) sifsel 1 selects pin sif2 for input (recommended for satellite tuner). 0 selects pin sif1 for input (terrestrial tv).
1999 dec 20 37 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.3 m onitor select register this register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be monitored. peak level refers to the magnitude of the maximum excursion of a signal. audio magnitude/phase is related to the fm demodulator output. phase information is provided, when it operates in fm mode, while magnitude is supplied in am mode. data can be read-out in the i 2 c-bus slave transmitter mode. by reading out level read-out registers (see section 10.4) the current peak level will be reset. table 17 subaddress 2 (note 1) note 1. the default setting at power-up is 0000 0000. table 18 monitor output table 19 signal source (note 1) note 1. the term crossbar refers to the digital selector, where level-adjusted signals from various sources are available. bit name value description 7 (msb) peakmon 1 selects the peak level of a source to be monitored 0 the last sample will be supplied 6 b6 0 default value 5 b5 0 default value 4b4 - monitor output (see table 18) 3b3 2b2 - signal source (see table 19) 1b1 0 (lsb) b0 b4 b3 monitor output 00 0 1 l input (channel 1, respectively) 1 0 r input (channel 2, respectively) b2 b1 b0 signal source 0 0 0 dc output of fm demodulator 0 0 1 audio magnitude/phase, fm demodulator output 0 1 0 crossbar input from fm/am channel 0 1 1 crossbar input from nicam channel 1 0 0 crossbar input from i 2 s1 channel 1 0 1 crossbar input from i 2 s2 channel 1 1 0 crossbar input from audio adc channel 1 1 1 input to main channel dac (without beeper) l input r input + 2 ------------------------------------------ -
1999 dec 20 38 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.4 c arrier 1 frequency register the three bytes together constitute a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency in accordance with the following formula: where: data = 24-bit frequency control word f mix = desired sound carrier frequency f clk = 12.288 mhz (clock frequency of mixer) 2 24 = 16777216 (number of steps in a 24-bit word size). example: a 5.5 mhz sound carrier frequency will be generated by sending the following sequence of data bytes to the tda9875a (data = 7509333 in decimal notation or 72555 in hexadecimal): 01110010 10010101 01010101. as three bytes are required to define a carrier frequency, execution of this command starts only after all bytes have been received. if an error occurs, e.g. a premature stop condition, partial data for this function is ignored. the default setting at power-up is 0000 0000 for all three bytes. most significant part at subaddress 3 and least significant part at subaddress 5 (see table 20). table 20 subaddresses 3 to 5 data f mix f clk --------- 2 24 = sub- address bit description 3 7 (msb) carrier 1 frequency; most signi?cant part 6 5 4 3 2 1 0 4 7 carrier 1 frequency 6 5 4 3 2 1 0 5 7 carrier 1 frequency; least signi?cant part 6 5 4 3 2 1 0 (lsb)
1999 dec 20 39 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.5 c arrier 2 frequency register same as for sound carrier 1, except for subaddresses (subaddresses 6 to 8). if the carrier 2 frequency register is used, it will be for either the second fm sound carrier of a terrestrial or satellite fm program or the nicam sound carrier. 10.3.6 d emodulator configuration register it is recommended to switch the fm sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. switching the identification off will reset the associated hardware to a defined state. table 21 subaddress 9 (note 1) notes 1. the default setting at power-up is 0000 0000. table 22 identi?cation mode table 23 filter bandwidth channel 1 and channel 2 bit name value description 7 (msb) idmod1 - these bits de?ne the response time after which a fm sound mode identi?cation result may be expected; the longer the time, the more reliable the identi?cation (see table 22) 6 idmod0 5 idarea 1 selects fm identi?cation frequencies in accordance with the speci?cation for korea 0 selects frequencies for europe (b/g and d/k standard) 4 filtbw1 - selects ?lter bandwidth (see table 23) 3 ch2mod1 - channel 2 receive mode: these bits control the hardware for the second sound carrier (see table 24); the nicam mode employs a wider bandwidth of the decimation ?lters than the fm mode 2 ch2mod0 1 filtbw0 - selects the ?lter bandwidth (see table 23) 0 (lsb) ch1mode 1 selects the hardware for the ?rst sound carrier to operate in am mode 0 fm mode is assumed; this applies to both terrestrial and satellite fm reception b7 b6 ident mode 0 0 slow 0 1 medium 1 0 fast 1 1 off/reset b4 b1 filter bandwidth filter modes ch1 ch2 0 0 narrow narrow recommended for nominal terrestrial broadcast conditions and sat with 2 carriers 0 1 extra wide narrow recommended only for high-deviation sat mono carriers (e.g. obsolete main channel on astra) 1 0 medium medium recommended for moderately overmodulated broadcast conditions 1 1 wide wide recommended for strongly overmodulated broadcast conditions
1999 dec 20 40 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 24 channel 2 receive mode 10.3.7 fm de - emphasis register this register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. bits b3 to b0 apply to sound carrier 1, bits b7 to b4 apply to sound carrier 2. in the event of a2 reception, both groups must be set to the same characteristics. table 25 subaddress 10 (note 1) note 1. the default setting at power-up is 0000 0000. 2. the fm de-emphasis gain is 0 db at 40 hz. table 26 de-emphasis sound carrier 2 table 27 de-emphasis sound carrier 1 b3 b2 channel 2 00 fm 01 am 1 0 nicam bit name value description 7 (msb) adeem2 1 activates the adaptive de-emphasis function, which is required for certain satellite fm channels. the standard fm de-emphasis must then be set to 75 m s (note 2). 0 the adaptive de-emphasis is off. 6b6 - time constant selection for fm de-emphasis (see table 26). 5b5 4b4 3 adeem1 1 activates the adaptive de-emphasis function, which is required for certain satellite fm channels. the standard fm de-emphasis must then be set to 75 m s (note 2). 0 the adaptive de-emphasis is off. 2b2 - time constant selection for fm de-emphasis (see table 27). 1b1 0 (lsb) b0 b6 b5 b4 de-emphasis 000 50 m s (europe) 001 60 m s 010 75 m s (m standard) 011 j17 100 off b2 b1 b0 de-emphasis 000 50 m s (europe) 001 60 m s
1999 dec 20 41 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.8 fm matrix register this register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification. table 28 subaddress 11 (note 1) note 1. the default setting at power-up is 0000 0000. table 29 dematrixing characteristics notes 1. ch1 input: audio signal from fm channel 1. 2. ch2 input: audio signal from fm channel 2. 3. for stereo korea the dematrix applies 6 db attenuation (see table 7). 010 75 m s (m standard) 011 j17 100 off bit name value description 7 (msb) b7 0 default value 6 b6 0 default value 5 b5 0 default value 4 b4 0 default value 3 b3 0 default value 2b2 - dematrixing characteristics (see table 29) 1b1 0 (lsb) b0 b2 b1 b0 l output r output mode 0 0 0 ch1 input; note 1 ch1 input; note 1 mono 1 0 0 1 ch2 input; note 2 ch2 input; note 2 mono 2 0 1 0 ch1 input; note 1 ch2 input; note 2 dual 0 1 1 ch2 input; note 2 ch1 input; note 1 dual swapped 1 0 0 2ch1 input - ch2 input ch2 input; note 2 stereo europe 1 0 1 stereo korea; note 3 b2 b1 b0 de-emphasis ch1 input ch2 input + 2 ----------------------------------------------------------- ch1 input ch2 input C 2 ---------------------------------------------------------- -
1999 dec 20 42 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.9 fm channel 1 level adjust register this register is used to correct for standard and station-dependent differences of signal levels. table 30 applies to sound carrier 1. table 30 subaddress 12 note 1. the default setting at power-up is 0000 0000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12 00010011 - 13 00010010 - 14 00010001 - 15 00010000 mute
1999 dec 20 43 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.10 fm channel 2 level adjust register this register is used to correct for standard and station-dependent differences of signal levels. table 31 applies to sound carrier 2 in its fm and am modes. in the event of a2, channels 1 and 2 should be adjusted to the same level. table 31 subaddress 13 note 1. the default setting at power-up is 0000 0000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12 00010011 - 13 00010010 - 14 00010001 - 15 00010000 mute
1999 dec 20 44 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.11 nicam configuration register the decision of whether auto-muting is permitted shall be taken by the controlling microcontroller based on information contained in the tda9875as status registers. thus, it depends on the strategy implemented in the software whether the auto-mute function is in accordance with nicam 728 ets revised for data applications or any other preference. the nicam de-emphasis gain is 0 db at 40 hz. table 32 subaddress 14 (note 1) notes 1. the default setting at power-up is 0000 0000. 2. the dcxo test mode is intended for checking the dcxo control range with the actually used pcb layout and crystal type. during the normal operating mode, the dcxo test mode should not be used. bit name value description 7 (msb) dcxopull 1 set to lower dcxo frequency during dcxo test mode. 0 set to higher dcxo frequency during dcxo test mode. 6 dcxotest 1 dcxo test mode on (available only during fm mode); note 2 0 dcxo normal mode on 5 b5 0 set logic to 0. 4 douten 1 enables the output of the nicam serial data stream from the dqpsk demodulator on pin nicam and of the associated clock on pin pclk 0 both outputs will be 3-stated. 3 0 set logic to 0. 2 amsel 1 the auto-mute function will switch the output sound from nicam l to the adc output select register. with the adc output select register the wanted signal source, e.g. the mono input, can be pre-set (see section 10.3.20). this is useful, if the am sound nicam l system is demodulated externally. 0 the auto-mute function will switch the output sound from nicam l to the am program on the internal ?rst sound carrier. 1 ndeem 1 switches the nicam j17 de-emphasis off. 0 switches the nicam j17 de-emphasis on. 0 (lsb) amute 1 automatic muting is disabled. this bit has only an effect when the second sound carrier is set to nicam. 0 enables the automatic switching between nicam and the program on the ?rst sound carrier (i.e. fm mono or am), dependent on the nicam bit error rate.
1999 dec 20 45 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.12 nicam level adjust register this register is used to correct for standard and station-dependent differences of signal levels. table 33 applies to both nicam sound outputs. table 33 subaddress 15 (note 1) note 1. the default setting at power-up is 000 00000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12 00010011 - 13 00010010 - 14 00010001 - 15 00010000 mute
1999 dec 20 46 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.13 nicam lower error limit register when the auto-mute function is enabled (bit amute in the nicam configuration register) and the nicam bit error count is lower than the value contained in this register, the nicam signal is selected (again) for reproduction (see section 10.3.14). table 34 subaddress 16 (notes 1 and 2) notes 1. the default setting at power-up is 0001 0100. 2. the lower bit error rate limit @ subaddress 16 1.74 10 - 5 . 10.3.14 nicam upper error limit register when the auto-mute function is enabled (bit amute in the nicam configuration register) and the nicam bit error count is higher than the value contained in this register, the signal of the first sound carrier (i.e. fm mono or am sound) or the external mono input (depending on bit amsel and adc output selection) is selected for reproduction. the difference between upper and lower error limit constitutes a hysteresis to avoid frequent switching between nicam and the program on the first sound carrier. table 35 subaddress 17 (notes 1 and 2) notes 1. the default setting at power-up is 0101 0000. 2. the upper bit error rate limit @ subaddress 17 1.74 10 - 5 . bit name value description 7 (msb) b7 - lower error limit value 6b6 5b5 4b4 3b3 2b2 1b1 0 (lsb) b0 bit name value description 7 (msb) b7 - upper error limit value 6b6 5b5 4b4 3b3 2b2 1b1 0 (lsb) b0
1999 dec 20 47 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.15 a udio mute control register when any of these bits are set to logic 1, the corresponding pair of output channels will be muted. a bit set to logic 0 allows normal signal output. there is a soft mute facility for the main and auxiliary output channels to provide click-free muting independent of the volume control. this is switched on/off by bits mutmain and mutaux. table 36 subaddress 18 (note 1) note 1. the default setting at power-up is 1111 1111. 10.3.16 dac output select register this register is used to define both the signal source to be entered into the dac and the mode of the digital matrix for signal selection. the dac is used for signal output from digital sources at analog outputs. the bits dacgain1 and dacgain2 can introduce some extra gain at the input to the dac; dacgain1 adds 3 db and dacgain2 adds 6 db of gain, respectively. the two combinations of fm and nicam apply to the (rare) condition that three different languages are being broadcast in an fm + nicam system. they allow for a two-out-of-three selection for external use, such as recording. bit name value description 7 (msb) muti 2 s2 1 mute i 2 s2 output 0 normal i 2 s2 output 6 muti 2 s1 1 mute i 2 s1 output 0 normal i 2 s1 output 5 mutdac 1 mute internal dac 0 normal internal dac 4 mutline 1 mute line outputs 0 normal line outputs 3 mutsc2 1 mute scart 2 outputs 0 normal scart 2 outputs 2 mutsc1 1 mute scart 1 outputs 0 normal scart 1 outputs 1 mutaux 1 mute auxiliary outputs 0 normal auxiliary outputs 0 (lsb) mutmain 1 mute main outputs 0 normal main outputs
1999 dec 20 48 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 37 subaddress 19 (note 1) note 1. the default setting at power-up is 0000 0000. table 38 extra gain setting table 39 dac output selection table 40 signal source selection bit name value description 7 (msb) dacgain2 - extra gain setting (see table 38) 6b6 - dac output selection (see table 39) 5b5 4b4 3 dacgain1 - extra gain setting (see table 38) 2b2 - signal source selection (see table 40) 1b1 0 (lsb) b0 b7 b3 gain (db) 00 0 01 3 10 6 11 9 b6 b5 b4 l output r output 0 0 0 l input r input 0 0 1 l input l input 0 1 0 r input r input 0 1 1 r input l input 100 b2 b1 b0 signal source left right 0 0 0 fm left fm right 0 0 1 nicam left nicam right 010 i 2 s1 left i 2 s1 right 011 i 2 s2 left i 2 s2 right 1 0 0 adc left adc right 1 0 1 avl left avl right 1 1 0 fm mono nicam m1 1 1 1 fm mono nicam m2 lr + 2 ------------- - lr + 2 ------------- -
1999 dec 20 49 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.17 scart 1 output select register this register is used to define both the signal source to be output at scart 1 and the output channel selector mode. table 41 subaddress 20 (note 1) note 1. the default setting at power-up is 0000 0001. table 42 output channel selection table 43 signal source selection bit name value description 7 (msb) b7 0 default value 6 sc1gain 1 activates the 3 db gain stage at the scart 1 output buffers. as any scart input passes a 3 db attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 db insertion loss when copying from scart 2 input to scart 1 output. however, that gain must be used with great care, as it will cause signal clipping at high input levels. 0 the audio signal output will be unchanged (0 db gain) 5b5 - output channel selection (see table 42) 4b4 3 b3 0 default value 2b2 - signal source selection (see table 43) 1b1 0 (lsb) b0 b5 b4 l output r output 0 0 l input r input 0 1 l input l input 1 0 r input r input 1 1 r input l input b2 b1 b0 signal source 0 0 0 scart 1 input 0 0 1 scart 2 input 0 1 0 external input 0 1 1 mono input 1 0 0 dac input
1999 dec 20 50 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.18 scart 2 output select register this register is used to define both the signal source to be output at scart 2 and the output channel selector mode. table 44 subaddress 21 (note 1) note 1. the default setting at power-up is 0000 0000. table 45 output channel selection table 46 signal source selection bit name value description 7 (msb) b7 0 6 sc2gain 1 activates the 3 db gain stage at the scart 2 output buffers. as any scart input passes a 3 db attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 db insertion loss when copying from scart 1 input to scart 2 output. however, that gain must be used with great care, as it will cause signal clipping at high input levels. 0 the audio signal output will be output (0 db gain) 5b5 - output channel selection (see table 45) 4b4 3 b3 0 default value 2b2 - signal source selection (see table 46) 1b1 0 (lsb) b0 b5 b4 l output r output 0 0 l input r input 0 1 l input l input 1 0 r input r input 1 1 r input l input b2 b1 b0 signal source 0 0 0 scart 1 input 0 0 1 scart 2 input 0 1 0 external input 0 1 1 mono input 1 0 0 dac input
1999 dec 20 51 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.19 l ine output select register by definition, the line output conveys the same signal as the main (loudspeaker) channel, but in a non-processed form. this register is used to characterize the signal to be output at the line output and define the output channel selector mode. table 47 subaddress 22 (note 1) note 1. the default setting at power-up is 0000 0000. table 48 output channel selection bit name value description 7 (msb) b7 0 set to logic 0 6 lingain 1 activates the 3 db gain stage at the line output buffers 0 audio signal will be output unchanged (0 db gain) 5b5 - output channel selection (see table 48) 4b4 3 b3 0 set to logic 0 2 b2 0 set to logic 0 1 b1 0 set to logic 0 0 (lsb) linsel 1 a signal from an analog source is being processed in the main channel for line output. analog signal sources comprise scart 1 input, scart 2 input, external input and mono input, i.e. any input to the adc. 0 a signal from a digital source is being processed in the main channel for line output. digital signal sources comprise fm, nicam, i 2 s1 input and i 2 s2 input. b5 b4 l output r output 0 0 l input r input 0 1 l input l input 1 0 r input r input 1 1 r input l input
1999 dec 20 52 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.20 adc output select register this register is used to define the signal source for the adc. there is no output channel selector, because all digital signal sinks of the adc have their own matrix. instead, a level adjustment facility for the adc output is provided. table 49 subaddress 23 (note 1) note 1. the default setting at power-up is 0000 0000. table 50 signal source selection bit name value description 7 (msb) b7 - signal source selection (see table 50) 6b6 5b5 4b4 - adc level adjust (see table 51) 3b3 2b2 1b1 0 (lsb) b0 b7 b6 b5 signal source 0 0 0 scart 1 input 0 0 1 scart 2 input 0 1 0 external input 0 1 1 mono input
1999 dec 20 53 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 51 adc level adjust (note 1) note 1. if the adc level adjust is set to 0 db a full-scale input signal to the adc results into a full-scale level of - 6dbatthe digital crossbar. b4 b3 b2 b1 b0 gain setting (db) 01111 +15 01110 +14 01101 +13 01100 +12 01011 +11 01010 +10 01001 +9 01000 +8 00111 +7 00110 +6 00101 +5 00100 +4 00011 +3 00010 +2 00001 +1 00000 0 11111 - 1 11110 - 2 11101 - 3 11100 - 4 11011 - 5 11010 - 6 11001 - 7 11000 - 8 10111 - 9 10110 - 10 10101 - 11 10100 - 12 10011 - 13 10010 - 14 10001 - 15 10000 mute
1999 dec 20 54 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.21 m ain channel select register this register is used to define both the signal source to be processed in the main (loudspeaker) channel and the mode of the digital matrix for signal selection. table 52 subaddress 24 (note 1) note 1. the default setting at power-up is 0000 0000. table 53 output channel selection table 54 signal source selection bit name value description 7 (msb) b7 0 default value 6b6 - output channel selection (see table 53) 5b5 4b4 3 b3 0 default value 2b2 - signal source selection (see table 54) 1b1 0 (lsb) b0 b6 b5 b4 l output r output 0 0 0 l input r input 0 0 1 l input l input 0 1 0 r input r input 0 1 1 r input l input 100 b2 b1 b0 signal source 0 0 0 fm input 0 0 1 nicam input 010 i 2 s1 input 011 i 2 s2 input 1 0 0 adc input lr + 2 ------------- - lr + 2 ------------- -
1999 dec 20 55 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.22 a udio effects register (m ain ) switching the avl off will reset the associated hardware to a defined state. when the signal source for the main channel is changed while the avl is on, the avl needs to be reset in order to avoid excessive settling times. this can be achieved by switching the avl off and on again. the pseudo stereo function is based on an all-pass filter. a 90 degrees phase shift occurs at the frequencies stated in table 57. there is a gain of 3 db in the left audio channel. table 55 subaddress 25 (note 1) note 1. the default setting at power-up is 0000 0000. table 56 spatial control setting table 57 pseudo control setting table 58 avl control mode bit name value description 7 (msb) b7 0 default value. 6 b6 0 default value. 5 spatial1 - these bits set the amount of the effect function (stereo base width expansion) for stereo signals in the main channel (see table 56). this function should be activated only in accordance with the result of the sound mode identi?cation. 4 spatial0 3 pseudo1 - these bits set the amount of the effect function (pseudo stereo) for mono signals in the main channel (see table 57). this function should be activated only in accordance with the result of the sound mode identi?cation. 2 pseudo0 1 avl1 - these bits set the mode of operation of the automatic volume level control function at the entrance to the main (loudspeaker) channel (see table 58). 0 (lsb) avl0 b5 b4 spatial setting (%) 0 0 off 01 30 10 40 11 52 b3 b2 pseudo setting (hz) 0 0 off 0 1 300 1 0 200 1 1 150 b1 b0 avl mode 0 0 off/reset 0 1 short decay 1 0 medium decay 1 1 long decay
1999 dec 20 56 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.23 v olume control registers (m ain ) these two registers control the volume setting of the main (loudspeaker) channel. the register at subaddress 26 applies to the left channel signal, while the register at subaddress 27 applies to the right channel signal. balance control is exercised by offsetting the left and right channel volume settings. table 59 subaddresses 26 and 27 msb lsb volume setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00011000 +24 00010111 +23 00010110 +22 00010101 +21 00010100 +20 00010011 +19 00010010 +18 00010001 +17 00010000 +16 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 11111111 - 1 11111110 - 2 11111101 - 3 11111100 - 4 11111011 - 5 11111010 - 6 11111001 - 7 11111000 - 8 11110111 - 9
1999 dec 20 57 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 11110110 - 10 11110101 - 11 11110100 - 12 11110011 - 13 11110010 - 14 11110001 - 15 11110000 - 16 11101111 - 17 11101110 - 18 11101101 - 19 11101100 - 20 11101011 - 21 11101010 - 22 11101001 - 23 11101000 - 24 11100111 - 25 11100110 - 26 11100101 - 27 11100100 - 28 11100011 - 29 11100010 - 30 11100001 - 31 11100000 - 32 11011111 - 33 11011110 - 34 11011101 - 35 11011100 - 36 11011011 - 37 11011010 - 38 11011001 - 39 11011000 - 40 11010111 - 41 11010110 - 42 11010101 - 43 11010100 - 44 11010011 - 45 11010010 - 46 11010001 - 47 11010000 - 48 msb lsb volume setting (db) b7 b6 b5 b4 b3 b2 b1 b0
1999 dec 20 58 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a note 1. the default setting at power-up is 1010 1100. 11001111 - 49 11001110 - 50 11001101 - 51 11001100 - 52 11001011 - 53 11001010 - 54 11001001 - 55 11001000 - 56 11000111 - 57 11000110 - 58 11000101 - 59 11000100 - 60 11000011 - 61 11000010 - 62 11000001 - 63 11000000 - 64 10111111 - 65 10111110 - 66 10111101 - 67 10111100 - 68 10111011 - 69 10111010 - 70 10111001 - 71 10111000 - 72 10110111 - 73 10110110 - 74 10110101 - 75 10110100 - 76 10110011 - 77 10110010 - 78 10110001 - 79 10110000 - 80 10101111 - 81 10101110 - 82 10101101 - 83 10101100 m ute (note 1) msb lsb volume setting (db) b7 b6 b5 b4 b3 b2 b1 b0
1999 dec 20 59 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.24 c ontour control register (m ain ) this register is used to apply the contour or loudness function (physiological volume control) to the left and right signal channels of the main channel by means of an extra bass boost. the gain setting must be chosen in accordance with the volume control setting for the main channel. for example, the contour gain could be incremented for every 5 db, or so, of decrease of the volume setting. this needs to be done by the microcontroller. the 0 db contour setting is equal to contour off. table 60 subaddress 28 note 1. the default setting at power-up is 0000 0000. msb lsb contour gain (db) b7 b6 b5 b4 b3 b2 b1 b0 00010010 18 00010001 17 00010000 16 00001111 15 00001110 14 00001101 13 00001100 12 00001011 11 00001010 10 00001001 9 00001000 8 00000111 7 00000110 6 00000101 5 00000100 4 00000011 3 00000010 2 00000001 1 00000000 0 (note 1)
1999 dec 20 60 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.25 b ass control register (m ain ) this register is used to apply bass control to the left and right signal channels of the main channel. table 61 subaddress 29 note 1. the default setting at power-up is 0000 0000. msb lsb bass setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12
1999 dec 20 61 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.26 t reble control register (m ain ) this register is used to apply treble control to the left and right signal channels of the main channel. table 62 subaddress 30 note 1. the default setting at power-up is 0000 0000. msb lsb treble setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12
1999 dec 20 62 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.27 a uxiliary channel select register this register is used to define both the signal source to be processed in the auxiliary (headphone) channel and the mode of the digital matrix for signal selection. table 63 subaddress 31 (note 1) note 1. the default setting at power-up is 0000 0000. table 64 output channel selection table 65 signal source selection bit name value description 7 (msb) b7 0 default value 6b6 - output channel selection (see table 64) 5b5 4b4 3 b3 0 default value 2b2 - signal source selection (see table 65) 1b1 0 (lsb) b0 b6 b5 b4 l output r output 0 0 0 l input r input 0 0 1 l input l input 0 1 0 r input r input 0 1 1 r input l input 100 b2 b1 b0 signal source 0 0 0 fm input 0 0 1 nicam input 010 i 2 s1 input 011 i 2 s2 input 1 0 0 adc input 1 0 1 avl input lr + 2 ------------- - lr + 2 ------------- -
1999 dec 20 63 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.28 v olume control registers (a uxiliary ) these two registers control the volume setting of the auxiliary (headphone) channel. the register at subaddress 32 applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal. balance control is exercised by offsetting the left and right channel volume settings. table 66 subaddresses 32 and 33 msb lsb volume setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00011000 +24 00010111 +23 00010110 +22 00010101 +21 00010100 +20 00010011 +19 00010010 +18 00010001 +17 00010000 +16 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 11111111 - 1 11111110 - 2 11111101 - 3 11111100 - 4 11111011 - 5 11111010 - 6 11111001 - 7 11111000 - 8 11110111 - 9 11110110 - 10
1999 dec 20 64 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 11110101 - 11 11110100 - 12 11110011 - 13 11110010 - 14 11110001 - 15 11110000 - 16 11101111 - 17 11101110 - 18 11101101 - 19 11101100 - 20 11101011 - 21 11101010 - 22 11101001 - 23 11101000 - 24 11100111 - 25 11100110 - 26 11100101 - 27 11100100 - 28 11100011 - 29 11100010 - 30 11100001 - 31 11100000 - 32 11011111 - 33 11011110 - 34 11011101 - 35 11011100 - 36 11011011 - 37 11011010 - 38 11011001 - 39 11011000 - 40 11010111 - 41 11010110 - 42 11010101 - 43 11010100 - 44 11010011 - 45 11010010 - 46 11010001 - 47 11010000 - 48 11001111 - 49 11001110 - 50 11001101 - 51 msb lsb volume setting (db) b7 b6 b5 b4 b3 b2 b1 b0
1999 dec 20 65 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a note 1. the default setting at power-up is 1010 1100. 11001100 - 52 11001011 - 53 11001010 - 54 11001001 - 55 11001000 - 56 11000111 - 57 11000110 - 58 11000101 - 59 11000100 - 60 11000011 - 61 11000010 - 62 11000001 - 63 11000000 - 64 10111111 - 65 10111110 - 66 10111101 - 67 10111100 - 68 10111011 - 69 10111010 - 70 10111001 - 71 10111000 - 72 10110111 - 73 10110110 - 74 10110101 - 75 10110100 - 76 10110011 - 77 10110010 - 78 10110001 - 79 10110000 - 80 10101111 - 81 10101110 - 82 10101101 - 83 10101100 m ute (note 1) msb lsb volume setting (db) b7 b6 b5 b4 b3 b2 b1 b0
1999 dec 20 66 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.29 b ass control register (a uxiliary ) this register is used to apply bass control to the left and right signal channels of the auxiliary channel. table 67 subaddress 34 note 1. the default setting at power-up is 0000 0000. msb lsb bass setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12
1999 dec 20 67 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.30 t reble control register (a uxiliary ) this register is used to apply treble control to the left and right signal channels of the auxiliary channel. table 68 subaddress 35 note 1. the default setting at power-up is 0000 0000. msb lsb treble setting (db) b7 b6 b5 b4 b3 b2 b1 b0 xxx01100 +12 xxx01011 +11 xxx01010 +10 xxx01001 +9 xxx01000 +8 xxx00111 +7 xxx00110 +6 xxx00101 +5 xxx00100 +4 xxx00011 +3 xxx00010 +2 xxx00001 +1 xxx00000 0 (note 1) xxx11111 - 1 xxx11110 - 2 xxx11101 - 3 xxx11100 - 4 xxx11011 - 5 xxx11010 - 6 xxx11001 - 7 xxx11000 - 8 xxx10111 - 9 xxx10110 - 10 xxx10101 - 11 xxx10100 - 12
1999 dec 20 68 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.31 f eature interface configuration register table 69 subaddress 36 (note 1) note 1. the default setting at power-up is 0000 0000. table 70 system clock frequency selection note 1. with 16.384 mhz the duty cycle is 33%. bit name value description 7 (msb) b7 0 default value 6 b6 0 default value 5 b5 0 default value 4 syscl1 - system clock frequency selection (see table 70) 3 syscl0 2 sysout 1 enables the output of a system (or master) clock signal at pin sysclk 0 the output will be off, thereby improving the emc performance 1i 2 sform 1 an msb-aligned (msb-?rst) serial output format is selected, i.e. a level change at pin ws indicates the beginning of a new audio sample 0 the standard i 2 s-bus output format is selected 0 (lsb) i 2 sout 1 enables the i 2 s-bus outputs (both serial data outputs plus serial bit clock and word select) in a format determined by bit i 2 sform; the tda9875a is then an i 2 s-bus master 0 the outputs mentioned will be 3-stated, thereby improving the emc performance b4 b3 sysclk output frequency (mhz) 0 0 256f s 8.192 0 1 384f s 12.288 1 0 512f s 16.384 (1) 1 1 768f s 24.576
1999 dec 20 69 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.32 i 2 s1 output select register this register is used to define both the signal source to be output at i 2 s1 and the mode of the digital matrix for signal selection. table 71 subaddress 37 (note 1) note 1. the default setting at power-up is 0000 0000. table 72 output selection table 73 signal source selection (note 1) note 1. the main and auxiliary channel outputs will not contain the beeper signal. bit name value description 7 (msb) b7 0 default value 6b6 - output selection (see table 72) 5b5 4b4 3 b3 0 default value 2b2 - signal source selection (see table 73) 1b1 0 (lsb) b0 b6 b5 b4 l output r output 0 0 0 l input r input 0 0 1 l input l input 0 1 0 r input r input 0 1 1 r input l input 100 b2 b1 b0 signal source 0 0 0 fm output 0 0 1 nicam output 010 i 2 s1 input 011 i 2 s2 input 1 0 0 adc output 1 0 1 avl output 1 1 0 auxiliary output 1 1 1 main output lr + 2 ------------- - lr + 2 ------------- -
1999 dec 20 70 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.33 i 2 s1 input level adjust register this register is used to adjust the input level at the i 2 s1 interface. left and right signal channel are treated identically. table 74 subaddress 38 note 1. the default setting at power-up is 0000 0000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12 00010011 - 13 00010010 - 14 00010001 - 15 00010000 mute
1999 dec 20 71 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.34 i 2 s1 output level adjust register this register is used to adjust the output level at the i 2 s1 interface. left and right signal channel are treated identically. table 75 subaddress 39 note 1. the default setting at power-up is 0000 0000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12 00010011 - 13 00010010 - 14 00010001 - 15 00010000 mute
1999 dec 20 72 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.35 i 2 s2 output select register this register is used to define both the signal source to be output at i 2 s2 and the mode of the digital matrix for signal selection. table 76 subaddress 40 (note 1) note 1. the default setting at power-up is 0000 0000. table 77 output selection table 78 signal source selection (note 1) note 1. the main and auxiliary channel outputs will not contain the beeper signal. bit name value description 7 (msb) b7 0 default value 6b6 - output selection (see table 77) 5b5 4b4 3 b3 0 default value 2b2 - signal source selection (see table 78) 1b1 0 (lsb) b0 b6 b5 b4 l output r output 0 0 0 l input r input 0 0 1 l input l input 0 1 0 r input r input 0 1 1 r input l input 100 b2 b1 b0 signal source 0 0 0 fm output 0 0 1 nicam output 010 i 2 s1 input 011 i 2 s2 input 1 0 0 adc output 1 0 1 avl output 1 1 0 auxiliary output 1 1 1 main output lr + 2 ------------- - lr + 2 ------------- -
1999 dec 20 73 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.36 i 2 s2 input level adjust register this register is used to adjust the input level at the i 2 s2 interface. left and right signal channel are treated identically. table 79 subaddress 41 note 1. the default setting at power-up is 0000 0000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12 00010011 - 13 00010010 - 14 00010001 - 15 00010000 mute
1999 dec 20 74 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.37 i 2 s2 output level adjust register this register is used to adjust the output level at the i 2 s2 interface. left and right signal channel are treated identically. table 80 subaddress 42 note 1. the default setting at power-up is 0000 0000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00001111 +15 00001110 +14 00001101 +13 00001100 +12 00001011 +11 00001010 +10 00001001 +9 00001000 +8 00000111 +7 00000110 +6 00000101 +5 00000100 +4 00000011 +3 00000010 +2 00000001 +1 00000000 0 (note 1) 00011111 - 1 00011110 - 2 00011101 - 3 00011100 - 4 00011011 - 5 00011010 - 6 00011001 - 7 00011000 - 8 00010111 - 9 00010110 - 10 00010101 - 11 00010100 - 12 00010011 - 13 00010010 - 14 00010001 - 15 00010000 mute
1999 dec 20 75 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.38 b eeper frequency control register this register is used to select from sample beeper oscillator frequencies. the beeper output signal is added to the main and auxiliary channel output dac. due to the frequency response of the audio dacs upsampling filters, the 25 khz beep is approximately 5 db louder than the 390 hz beep. table 81 subaddress 43 (note 1) note 1. the default setting at power-up is 0000 0000. 10.3.39 b eeper volume control register this register is used to set the beeper volume. the gain setting is relative to digital full-scale at the input to the main and auxiliary channel output dacs. the beeper volume is independent of any other volume setting. the beeper signal is added to the main and auxiliary channel output signals in the 2 f s domain. the beeper volume should be set with great care, when the audio signals in the main and auxiliary channels are close to digital full-scale, to avoid output signal distortion due to overload. msb lsb generated frequency (hz) b7 b6 b5 b4 b3 b2 b1 b0 00000111 25000 00000110 7040 00000101 3580 00000100 1770 00000011 1270 00000010 900 00000001 640 00000000 390
1999 dec 20 76 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 82 subaddress 44 note 1. the default setting at power-up is 0010 0000. msb lsb gain setting (db) b7 b6 b5 b4 b3 b2 b1 b0 00000000 0 00111111 - 3 00111110 - 6 00111101 - 9 00111100 - 12 00111011 - 15 00111010 - 18 00111001 - 21 00111000 - 24 00110111 - 27 00110110 - 30 00110101 - 33 00110100 - 36 00110011 - 39 00110010 - 42 00110001 - 45 00110000 - 48 00101111 - 51 00101110 - 54 00101101 - 57 00101100 - 60 00101011 - 63 00101010 - 66 00101001 - 69 00101000 - 72 00100111 - 75 00100110 - 78 00100101 - 81 00100100 - 84 00100011 - 87 00100010 - 90 00100001 - 93 00100000 m ute (note 1)
1999 dec 20 77 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.3.40 b ass boost control register this register is used to select from a few sample bass boost settings to modify the frequency characteristics of the main channel (shelving filter). bits b3 to b0 apply to the left channel, bits b7 to b4 apply to the right channel. this function must be used with care in order to avoid clipping distortion at high volume settings. more sophisticated control of the bass boost filter can be exercised in the expert mode (see section 10.5). the user then has full control over this second-order filter and can, within limits, realize bass equalizers with arbitrary centre frequencies, q factors and boost/cut settings. table 83 subaddress 45 (note 1) note 1. the default setting at power-up is 0000 0000. table 84 gain setting right channel bit name value description 7 (msb) b7 - gain setting of right channel (see table 84) 6b6 5b5 4b4 3b3 - gain setting of left channel (see table 85) 2b2 1b1 0 (lsb) b0 b7 b6 b5 b4 gain setting (db) corner frequency (hz) 1010 20 350 1001 18 350 1000 16 350 0111 14 350 0110 12 350 0101 10 350 0100 8 350 0011 6 350 0010 4 350 0001 2 350 0000 0 350
1999 dec 20 78 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 85 gain setting left channel b3 b2 b1 b0 gain setting (db) corner frequency (hz) 1010 20 350 1001 18 350 1000 16 350 0111 14 350 0110 12 350 0101 10 350 0100 8 350 0011 6 350 0010 4 350 0001 2 350 0000 0 350
1999 dec 20 79 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.4 slave transmitter mode as a slave transmitter, the tda9875a provides 13 registers with status information and data, a part of which is for philips internal purposes only. these registers can be accessed by means of subaddresses. table 86 general format for reading data from the tda9875a table 87 explanation of tables 86 and 88 reading of data can start at any valid subaddress. it is allowed to read more than 1 data byte per transmission from the tda9875a. in this situation, the subaddress is automatically incremented after each data byte, which results in reading the sequence of data bytes from successive register locations, starting at subaddress. table 88 format of a transmission using automatic incrementing of subaddresses note 1. n data bytes with auto-increment of subaddresses. each data byte in a read sequence, except for the last one, is acknowledged with am (acknowledge by the master). the subaddresses wrap around from decimal 255 to 0. if an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. ff in hexadecimal notation. s slave address 0 ack subaddress ack sr slave address 1 ack data nam p bit function s start condition slave address 7-bit device address 0 data direction bit (write to device) ack acknowledge (by the slave) subaddress address of register to read from sr repeated start condition 1 data direction bit (read from device) data data byte read from register nam not acknowledge (by the master) am acknowledge (by the master) p stop condition s slave address 0 ack subaddress ack sr slave address 1 ack data byte am (1) data nam p
1999 dec 20 80 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 89 overview of the slave transmitter registers (note 1) notes 1. x indicates a bit that has not been assigned to a function. this bit is reserved for future extensions. 2. registers from subaddress 251 to 255 are for philips internal purposes only. they are considered as a set of registers for the identification of individual members and some key parameters in a family of devices. the following sub-sections provide a detailed description of the slave transmitter registers. subaddress (decimal) data function msb lsb 0 ssssssssde vice status (power-on, identi?cation, etc.) 1 ssssssss nicam status 2 eeeeeeee nicam error count 3 dddddddd additional data (lsb) 4 c c x c c d d d additional data (msb) 5 lllllllllevel read-out (msb) 6 lllllllllevel read-out (lsb) 7 xxxccccc sif level 251 aaaaaaaa test register 3; note 2 252 aaaaaaaa test register 2; note 2 253 aaaaaaaa test register 1; note 2 254 ddddddddde vice identi?cation code 255 ssssssss software identi?cation code
1999 dec 20 81 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.4.1 d evice status register table 90 subaddress 0 bit name value description 7 (msb) p2in - this bit re?ects the status of the corresponding general purpose port of pin p2 (see section 10.3.2). 6 p1in - this bit re?ects the status of the corresponding general purpose port of pin p1 (see section 10.3.2). 5 rssf 1 reserve sound switching ?ag: this bit is a copy of the c4 bit in the nicam status register. it indicates that the fm (or am for standard l) sound matches the digital transmission and auto-muting should be enabled. 0 auto-muting should be disabled, as analog and digital sound are different. 4 amstat 1 auto-mute status: it indicates that the auto-muting function has switched from nicam to the program of the ?rst sound carrier (i.e. fm mono or am in the nicam l system) or to the adc (depending on bit amsel). 0 auto-muting function has not switched. 3 vdsp 1 indicates that digital transmission is a sound source (nicam). 0 the transmission is either data or currently unde?ned format (nicam). 2 iddua - this bit is logic 1 if an fm dual-language signal has been identi?ed. when neither idste nor iddua are set, the received signal has to be assumed to be fm mono. 1 idste - this bit is logic 1 if an fm stereo signal has been identi?ed. 0 (lsb) por - power fail bit: the power supply for the digital part of the device, v ddd2 , has temporarily been lower than the speci?ed lower limit. if this is detected an initialization of the tda9875a has to be carried out to ensure a reliable operation.
1999 dec 20 82 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.4.2 nicam status register the tda9875a does not support the extended control modes. therefore, the program of the first sound carrier (i.e. fm mono or am) is selected for reproduction in case bit c3 is set to logic 1, independent of bit amute in the nicam configuration register being set or not. when a nicam transmitter is switched off, the device will lose synchronization. in this situation the program of the first sound carrier is selected for reproduction, independent of bit amute being set or not. table 91 subaddress 1 10.4.3 nican error count register bits b7 to b0 contain the number of errors occurring in the previous 128 ms period. the register is updated every 128 ms. table 92 subaddress 2 bit name value description 7 (msb) c4 - application control bits (c1 to c4 in the nicam transmission) 6c3 5c2 4c1 3 osb 1 indication that the device has both frame and c0 (16 frame) synchronization 0 the audio output from the nicam part should be digital silence 2 cfc 1 indication of a con?guration change at the 16 frame (c0) boundary 0 no con?guration change 1 s/mb 1 indication of nicam stereo mode 0 no nicam stereo mode 0 (lsb) d/sb 1 indication nicam dual mono mode 0 no nicam dual mono mode bit name value description 7 (msb) b7 - number of errors 6b6 5b5 4b4 3b3 2b2 1b1 0 (lsb) b0
1999 dec 20 83 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.4.4 a dditional data registers these two bytes provide information on the additional data bits. table 93 subaddress 3 table 94 subaddress 4 bit name value description 7 (msb) ad7 - comprise the additional data word 6 ad6 5 ad5 4 ad4 3 ad3 2 ad2 1 ad1 0 (lsb) ad0 bit name value description 7 (msb) ovw 1 new additional data bits are written to the ic without the previous bits being read 0 no bits are written 6 sad 1 new additional data is written into the ic 0 this bit is set to logic 0 when the additional data bits are read 5x - dont care 4 ci1 - these are ci bits decoded by majority logic from the parity checks of the last ten samples in a frame 3 ci2 2 ad10 - comprise the additional data word 1 ad9 0 (lsb) ad8
1999 dec 20 84 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.4.5 l evel read - out registers these two bytes constitute a word that provides data from a location that has been specified with the monitor select register. the most significant byte of the data is stored at subaddress 5. if peak-level monitoring has been selected, the peak-level monitoring register is cleared and monitoring resumes after its contents has been transferred to these two bytes. table 95 subaddresses 5 and 6 10.4.6 sif level register when the sif agc is on, bits b4 to b0 of this register contain a number that gives an indication of the sif input level. that number corresponds to the agc gain register setting (see section 10.3.1). when the sif agc is off, this register returns the contents of the agc gain register. table 96 subaddress 7 10.4.7 t est register 3 this register contains, as a binary number, the highest memory address used for the coefficient ram (cram, expert mode). table 97 subaddress 251 10.4.8 t est register 2 this register contains, as a binary number, the highest subaddress used for slave receiver registers. table 98 subaddress 252 sub- address bit description 5 7 (msb) most signi?cant bit or sign bit 6 5 4 3 2 1 0 (lsb) 6 7 (msb) 6 5 4 3 2 1 0 (lsb) least signi?cant bit bit name value description 7 (msb) b7 x bit not assigned 6 b6 x bit not assigned 5 b5 x bit not assigned 4b4 - indication of sif input level 3b3 2b2 1b1 0 (lsb) b0 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 01111111 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 00101101
1999 dec 20 85 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 10.4.9 t est register 1 this register contains, as a binary number, the highest subaddress used for slave transmitter (status) registers. table 99 subaddress 253 10.4.10 d evice identification code there will be several devices in the digital tv sound processor family. this byte is used to identify the individual family members. table 100 subaddress 254 10.4.11 s oftware identification code it is likely that during the life time of this family of devices several versions of the dsp software will be made, e.g., to accommodate new application concepts, respond to customer wishes, etc. this byte is used to identify the different releases. table 101 subaddress 255 10.5 expert mode in addition to the slave receiver and slave transmitter modes previously described, there is a special expert mode that gives direct write access to the internal cram of the dsp. in this mode, transferred data contain 12-bit coefficients. as these coefficients bypass on-chip coefficient look-up tables for many functions, they directly influence the processing of signals within the dsp. this mode must be used with great care. it can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses. as the coefficients do not fit into one data byte, they have to be split and arranged (see table 104). the most significant bit is transferred first. the general format described in table 104 shows the minimum number of data bytes required, i.e. two bytes for the transfer of a single coefficient. should more than one coefficient be sent, then the cram address will be automatically incremented after each coefficient, resulting in writing the sequence of coefficients into successive memory locations, starting at cram address. a transmission can start with any valid cram address. if two coefficients are to be transferred, they are arranged as shown in table 105. with any odd number of coefficients to be transferred, the least significant nibble of the last byte is regarded as containing dont care data. as the transfer of coefficients cannot be accomplished within one audio sample period, it is necessary that received coefficients be buffered and made active all at the same time to avoid audio signal transients. the receive buffer is designed to store up to 8 coefficients in addition to the cram address. each byte that fits into the buffer is acknowledged with ack (acknowledge). if an attempt is made to write more coefficients than the buffer can store, the device acknowledges with nack (not acknowledge) and any further coefficients are ignored. coefficients that are already in the receive buffer remain intact. an expert mode transfer ends when the i 2 c-bus stop condition or a repeated start condition has been detected. only those coefficients that have been received during the last transmission will then be copied from the buffer to the cram. to make efficient and correct use of the expert mode, it is recommended to transfer all coefficients for any one function in a single transmission. there is no checking of memory addresses and the automatic incrementing of addresses does not stop at the highest used cram address. the user of this expert mode must be fully acquainted with the relevant procedures. more information concerning the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be supplied on request at a later date. msb lsb b7 b6 b5 b4 b3 b2 b1 b0 00000111 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 00000010 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 00000010
1999 dec 20 86 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a table 102 general format for entering the expert mode and writing coef?cients into the tda9875a table 103 explanation of table 102 table 104 general format (notes 1, 2 and 3) notes 1. x = dont care. 2. mst = most significant third. 3. lst = least significant third. table 105 transfer of two coef?cients s slave address 0 ack 10000000 ack cram address ack data ack data ack p bit function s start condition slave address 7-bit device address 0 data direction bit (write to device) ack acknowledge 10000000 pattern to enter the expert mode cram address start address of coef?cient ram to write to data data byte containing part of a coef?cient p stop condition byte data description 1 data byte aaaaaaaa2 mst of 1st coef?cient 2 data byte aaaa xxxx1 lst of 1st coef?cient byte data description 1 data byte aaaaaaaa2 mst of 1st coef?cient 2 data byte aaaabbbb1 lst of 1st coef?cient + 1 mst of 2nd coef?cient 3 data byte bbbbbbbb2 lst of 2nd coef?cient
1999 dec 20 87 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 11 i 2 s-bus description the feature interface of the tda9875a contains two serial audio inputs and outputs and associated clock signals. it can be used to supply, for example, audio signals from received tv programs to a digital audio output device (aes/ebu format), or import serial audio signals from other sources for reproduction through the tv sets loudspeaker and/or headphone channels. apart from such simple data input or output, it is also possible to run audio signals through an external dsp, which performs some additional functions, such as room simulation, dolby surround pro logic etc. and feed those signals back into the loudspeaker and/or headphone channels of the tda9875a. two serial audio formats are supported at the feature interface, i.e. the i 2 s-bus format and a very similar msb-aligned format. the difference is illustrated in fig.9. in both formats the left audio channel of a stereo sample pair is output first and is placed on the serial data line (sdi for input, sdo for output) when the word select line (ws) is low. data is written at the trailing edge of sck and read at the leading edge of sck. the most significant bit is sent first. at power-up, the outputs of the feature interface are 3-stated to reduce emc and allow for combinations with other ics. if output is desired, it has to be activated by means of an i 2 c-bus command. when the output is enabled, the serial audio data can be taken from pins sdo1 and sdo2. depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language sound on either output. the word select output is clocked with the audio sample frequency at 32 khz. the serial clock output (sck) is clocked at a frequency of 2.048 mhz. this means, that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. depending again on the signal source, the number of significant bits on the serial data outputs, sdo1 and sdo2, is between 14 and 18. apart from just feeding a digital audio device, such as a dac or an aes/ebu transmitter, the serial data outputs can be connected directly to the serial inputs (loop-back connection) or first to an external device, e.g. a feature dsp such as the saa7710 and then back to the serial inputs. in all of these configurations, the sck and ws clocks will be generated by the tda9875a, which then is the i 2 s-bus master. the serial data inputs, sdi1 and sdi2, are active at all times, independent of the serial data outputs being on or off. when the serial data outputs are off (either after power-up or via the appropriate i 2 c-bus command) serial data and clocks ws and sck from a separate digital audio source can be fed into the tda9875a, be processed and output in accordance with internal selector positions, provided that the following criteria are met: 32 khz audio sample frequency 32 clock bits per sample external timing and data synchronized to tda9875a. in such cases, the external source is the i 2 s-bus master and the tda9875a is the i 2 s-bus slave. to support synchronization of external devices or as a master clock for them, a system clock output, sysclk, is available from the tda9875a. at power-up it is off. it can be enabled and the output frequency set via an i 2 c-bus command. available output frequencies are 8.192, 12.288, 16.384 and 24.576 mhz.
1999 dec 20 88 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a handbook, full pagewidth mgk112 sck ws sd lsb msb one sample lsb msb handbook, full pagewidth mgk113 sck ws sd lsb msb one sample lsb msb fig.9 serial audio interface formats. a. i 2 s-bus format. b. msb-aligned format.
1999 dec 20 89 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 12 application information handbook, full pagewidth 1.5 w r2 10 k w r1 1 m f c6 c2 47 pf c4 47 pf c3 100 nf c5 47 m f c1 4.7 m f v ddd2 v dda v ssa1 test1 i ref v dec1 v ssa3 mor auxol pcapl pcapr scol2 scor2 scol1 scor1 i.c. i.c. i.c. scil2 scil1 scir1 scir2 i.c. v ref3 v ref2 v ref(n) v ref(p) v ssa2 v dec2 v ssd3 v ssa4 v ssd2 auxor lor nicam pclk addr1 scl sda sifsat p2 creset xtali xtalo addr2 sif1 siftv p1 sif2 v ddd1 v ssd1 v ssd4 v ref1 sysclk sck ws sdo2 sdo1 sdi2 sdi1 monoin extir extil test2 lol mol 61 60 59 58 57 56 55 54 53 52 51 48 47 50 49 46 43 42 41 45 44 40 39 38 35 34 33 37 36 62 63 64 4 5 6 7 8 9 10 11 12 13 14 17 18 15 16 19 22 23 24 20 21 25 26 27 30 31 32 28 470 nf c7 470 nf c8 470 nf c9 29 3 2 1 1.5 w 2.2 w 2.2 m f 47 m f 2.2 m f c33 c31 c28 c32 2.2 m f c30 2.2 m f c27 2.2 m f c25 2.2 m f c20 2.2 m f c19 2.2 m f c18 47 m f c15 47 m f c14 4.7 m f c16 2.2 m f c17 47 m f c21 10 nf c29 10 nf c26 10 nf c24 10 nf c23 10 nf c13 330 nf c12 330 nf c11 330 nf c10 330 nf c22 10 nf 2.2 m f 47 m f c34 c35 r19 r8 + 5 v + 5 v + 5 v 15 k w r7 r6 15 k w r3 15 k w r5 15 k w r4 270 w 24.576 mhz mhb601 tda9875a (tda9875ah) (53) 61 (52) 60 (51) 59 (50) 58 (49) 57 (48) 56 (47) 55 (46) 54 (45) 53 (44) 52 (43) 51 (40) 48 (39) 47 (42) 50 (41) 49 (38) 46 (35) 43 (34) 42 (33) 41 (37) 45 (36) 44 (32) 40 (31) 39 (30) 38 (27) 35 (26) 34 (25) 33 (29) 37 (28) 36 (54) 62 (55) 63 (56) 64 4 (60) 5 (61) 6 (62) 7 (63) 8 (64) 9 (1) 10 (2) 11 (3) 12 (4) 13 (5) 14 (6) 17 (9) 18 (10) 15 (7) 16 (8) 19 (11) 22 (14) 23 (15) 24 (16) 20 (12) 21 (13) 25 (17) 26 (18) 27 (19) 30 (22) 31 (23) 32 (24) 28 (20) 29 (21) 3 (59) 2 (58) 1 (57) fig.10 schematic for measurements. the pin numbers given in parenthesis refer to the tda9875ah version.
1999 dec 20 90 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a handbook, full pagewidth mhb602 1 w r5 10 k w r3 2.2 k w r4 1 m f c7 c3 47 pf c5 47 pf c4 100 nf c6 470 nf c2 470 nf tda9875a (tda9875ah) v ddd2 v dda v ssa1 test1 i ref v dec1 v ssa3 mor auxol pcapl pcapr scol2 scor2 scol1 scor1 i.c. i.c. i.c. scil2 scil1 scir1 scir2 i.c. v ref3 v ref2 v ref(n) v ref(p) v ssa2 v dec2 v ssd3 v ssa4 v ssd2 auxor lor nicam pclk addr1 scl sda sifsat p2 creset xtali xtalo addr2 sif1 siftv p1 sif2 v ddd1 v ssd1 v ssd4 v ref1 sysclk sck ws sdo2 sdo1 sdi2 sdi1 monoin extir extil test2 lol mol (53) 61 (52) 60 (51) 59 (50) 58 (49) 57 (48) 56 (47) 55 (46) 54 (45) 53 (44) 52 (43) 51 (40) 48 (39) 47 (42) 50 (41) 49 (38) 46 (35) 43 (34) 42 (33) 41 (37) 45 (36) 44 (32) 40 (31) 39 (30) 38 (27) 35 (26) 34 (25) 33 (29) 37 (28) 36 (54) 62 (55) 63 (56) 64 4 (60) 5 (61) 6 (62) 7 (63) 8 (64) 9 (1) 10 (2) 11 (3) 12 (4) 13 (5) 14 (6) 17 (9) 18 (10) 15 (7) 16 (8) 19 (11) 22 (14) 23 (15) 24 (16) 20 (12) 21 (13) 25 (17) 26 (18) 27 (19) 30 (22) 31 (23) 32 (24) 28 (20) 470 nf c8 470 nf c9 470 nf c10 29 (21) 3 (59) 2 (58) 1 (57) 1 w 2.2 w 2.2 m f 470 nf 2.2 m f c39 c36 c32 470 pf c38 470 pf c40 c37 2.2 m f c35 2.2 m f c33 2.2 m f c29 2.2 m f c25 2.2 m f c23 2.2 m f c21 47 m f c16 47 m f c15 470 nf c17 2.2 m f c19 47 m f c26 10 nf c34 10 nf c31 10 nf c30 10 nf c20 470 pf c24 470 pf c22 470 pf c18 470 pf c28 10 nf c14 330 nf c13 330 nf c12 330 nf c11 330 nf c27 10 nf 2.2 m f 470 nf c41 c42 r13 r12 + 5 v + 5 v + 5 v 15 k w r11 r10 15 k w r7 15 k w r9 15 k w r8 270 w 24.576 mhz l9 l8 l7 l6 2.2 k w r6 l5 l4 l3 100 w r1 l1 100 w r2 l2 47 m f c1 0 v power + 5 v fig.11 schematic for application. l1 to l9 are ferrite beads. the pin numbers given in parenthesis refer to the tda9875ah version.
1999 dec 20 91 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 13 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot274-1 ms-021 95-02-04 99-12-27 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 58.67 57.70 17.2 16.9 3.2 2.8 0.18 1.778 19.05 19.61 19.05 20.96 19.71 1.73 5.84 0.51 4.57 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z 64 1 33 32 b e pin 1 index a max. 12 a min. a max. sdip64: plastic shrink dual in-line package; 64 leads (750 mil) sot274-1
1999 dec 20 92 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 0.8 17.45 16.95 1.2 0.8 7 0 o o 0.16 0.10 0.16 1.60 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.03 0.73 sot393-1 ms-022 97-08-04 99-12-27 d (1) (1) (1) 14.1 13.9 h d 17.45 16.95 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 16 y c e h a 2 d z d a z e e v m a 1 64 49 48 33 32 17 x b p d h b p v m b w m w m 0 5 10 mm scale pin 1 index qfp64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm sot393-1 a max. 3.00
1999 dec 20 93 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 14 soldering 14.1 introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 14.2 through-hole mount packages 14.2.1 s oldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 m anual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 14.3 surface mount packages 14.3.1 r eflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 14.3.2 w ave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.3.3 m anual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 dec 20 94 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 14.4 suitability of ic packages for wave, re?ow and dipping soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. mounting package soldering method wave reflow (1) dipping through-hole mount dbs, dip, hdip, sdip, sil suitable (2) - suitable surface mount bga, sqfp not suitable suitable - hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (3) suitable - plcc (4) , so, soj suitable suitable - lqfp, qfp, tqfp not recommended (4)(5) suitable - ssop, tssop, vso not recommended (6) suitable -
1999 dec 20 95 philips semiconductors product speci?cation digital tv sound processor (dtvsp) tda9875a 15 definitions 16 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 17 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 68 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 printed in the netherlands 545004/02/pp 96 date of release: 1999 dec 20 document order number: 9397 750 06065

▲Up To Search▲

Price & Availability of TDA9875AV2

	To Download TDA9875AV2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .